CS 61C Quiz - Week 9

Current time: Sat Jan 20 05:16:34 2018

Deadline: Sun Mar 23 23:59:00 2008

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Question 1:

Why does it make it easier to design with flip-flops if the hold time 
is less than the clk-to-q delay?

Question 2:

Why is it harder to go from a truth table to a gate level description? 
Not impossible, just harder. 

Question 3:

How would you extend the design on p.300 (of P & H) to handle J-Type 
instructions? Do not worry about the control, or drawing a schematic. 
Just generally what blocks/wires would you need to add where. 

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