Project 4: Processor Design

CS61C Spring 2012

Due Sunday, April 15th, 2012 at 11:59 PM

TA in charge: Ian Vonseggern

Based on original spec by Ben Sussman and Brian Zimmer, and modified spec of Albert Chae, Paul Pearce, Noah Johnson, Justin Hsia, Conor Hughes, and Anirudh Todi.
Much thanks to Conor Hughes for an excellent assembler and autograder.

Post any questions or comments to Piazza.

This project spec is ridiculously long, but don't fret! We've spelled out many things in excruciating detail, so if you just take things one-by-one, it won't be as bad as it looks.

We are also providing a set of abridged project notes to look at. These will NOT substitute for reading through the actual project specs, but can be used as a quick reference later on.

Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission

Updates and Clarifications

Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission


In this project you will be using Logisim to create a 16-bit two-cycle processor. It is similar to MIPS, except that both the datapath and the instructions are 16-bits wide, it has only 4 registers, and memory addresses represent 16-bit words instead of 8-bit bytes (word-addressed instead of byte-addressed).

Please read this document CAREFULLY as there are key differences between the processor we studied in class and the processor you will be designing for this project.

Before you begin, copy the start kit to your home directory (and then possibly to your own machine):

    $ cp -r ~cs61c/proj4StartKit ~/proj4


Your processor will have a 2-stage pipeline:

  1. Instruction Fetch: An instruction is fetched from the instruction memory.
  2. Execute: The instruction is decoded, executed, and committed (written back). This is a combination of the remaining stages of a normal MIPS pipeline.

You should note that data hazards do NOT pose a problem for this design, since all accesses to all sources of data happens only in a single pipeline stage. However, there are still control hazards to deal with. Our ISA does not expose branch delay slots to software. This means that the instruction immediately after a branch or jump is not necessarily executed if the branch is taken. This makes your task a bit more complex. By the time you have figured out that a branch or jump is in the execute stage, you have already accessed the instruction memory and pulled out (possibly) the wrong instruction. You will therefore need to "kill" instructions that are being fetched if the instruction under execution is a jump or a taken branch. Instruction kills for this project MUST be accomplished by MUXing a nop into the instruction stream and sending the nop into the Execute stage instead of using the fetched instruction. Notice that 0x0000 is a nop instruction; please use this, as it will simplify grading and testing. You should only kill if a branch is taken (do not kill otherwise), but do kill on every type of jump.

Because all of the control and execution is handled in the Execute stage, your processor should be more or less indistinguishable from a single-cycle implementation, barring the one-cycle startup latency and the branch/jump delays. However, we will be enforcing the two-pipeline design. If you are unsure about pipelining, it is perfectly fine (maybe even recommended) to first implement a single-cycle processor. This will allow you to first verify that your instruction decoding, control signals, arithmetic operations, and memory accesses are all working properly. From a single-cycle processor you can then split off the Instruction Fetch stage with a few additions and a few logical tweaks. Some things to consider:

You might also notice a bootstrapping problem here: during the first cycle, the instruction register sitting between the pipeline stages won't contain an instruction loaded from memory. How do we deal with this? It happens that Logisim automatically sets registers to zero on reset; the instruction register will then contain a nop (you can consider this start-up a CPU stall). We will allow you to depend on this behavior of Logisim. Remember to go to Simulate --> Reset Simulation (Ctrl+R) to reset your processor.

Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission


Approach this project like you would any coding assignment: construct it piece by piece and test each component early and often!

Tidyness and readability (i.e. labeling, neat wiring) is much appreciated by the graders, and a portion of your grade will reflect this.

1) Register File [show]

2) Arithmetic Logic Unit (ALU) [show]

3) Processor [show]

3a) Data Memory [show]

3b) Output Devices [show]

4) Test Code [show]

*) Extra for Experts [show]

Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission

Instruction Set Architecture (ISA)

You will be implementing a simple 16-bit processor with four registers ($r0-$r3). It will have separate data and instruction memory. Because this is a 16-bit architecture, our words are 16 bits wide, unlike the 32-bit MIPS ISA we have been studying in class. For the remainder of this document, a WORD refers to 16 bits. Each of the four registers is big enough to hold ONE word.

IMPORTANT: Because of the limitations of Logisim (and to make things simpler), our memories will be word-addressed (16 bits), unlike MIPS, which is byte-addressed (8 bits).

The instruction encoding is given below. Your processor will pull out a 16-bit value from instruction memory and determine the meaning of that instruction by looking at the opcode (the top four bits, which are bits 15-12). If the instruction is an R-type (i.e. opcode == 0), then you must also look at the funct field.

Notice how we do not use all 16 possible opcodes, nor did we use all 64 R-type instructions. Your project only has to work on these specified instructions. This way the project is shorter and easier.

15-12 11 10 9 8 7 6 5 4 3 2 1 0
0 rs rt rd funct See R-type Instructions
1 rs rt immediate (unsigned) disp: DISP[imm] = $rs
2 rs rt immediate (unsigned) lui:  $rt = imm << 8
3 rs rt immediate (unsigned) ori:  $rt = $rs | imm
4 rs rt immediate (signed) addi: $rt = $rs + imm
5 rs rt immediate (unsigned) andi: $rt = $rs & imm
6 target address jal into $r3
7 target address j:     jump to target address
8 rs unused jr:   PC = $rs
9 rs rt offset (signed) beq
10 rs rt offset (signed) bne
11 rs rt immediate (signed) lw:   $rt = MEM[$rs + imm]
12 rs rt immediate (signed) sw:   MEM[$rs+imm] = $rt

R-Type Instructions
funct Instruction
0 or:   $rd = $rs | $rt
1 and:  $rd = $rs & $rt
2 add:  $rd = $rs + $rt
3 sub:  $rd = $rs - $rt
4 sllv: $rd = $rs << $rt
5 srlv: $rd = $rs >> $rt
6 srav: $rd = $rs >> $rt
7 slt:  $rd = ($rs < $rt) ? 1 : 0
8 addp8: $rd = {$rs[15:8] + $rt[15:8] , $rs[7:0] + $rt[7:0] }
9 subp8: $rd = {$rs[15:8] - $rt[15:8] , $rs[7:0] - $rt[7:0] }
10 sltp8: $rd = {7'b0 , ($rs[15:8] < $rt[15:8] ? 'b1 : 'b0) , 7'b0 , ($rs[7:0] < $rt[7:0] ? 'b1 : 'b0)}

Some specifics on selected instructions:





Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission

Logisim Notes

It is strongly recommended that you download and run Logisim on your local machine while developing your processor to avoid overwhelming the instructional machines. Though Logisim is relatively stable compared to prior semesters, it is still recommended that you save often and also make backup copies of your .circ files early and often. The official version of Logisim we will be using for evaluation is v2.7.1.

If you are having trouble with Logisim, RESTART IT and RELOAD your circuit! Don't waste your time chasing a bug that is not your fault. However, if restarting doesn't solve the problem, it is more likely that the bug is a flaw in your project. Please post to Piazza about any crazy bugs that you find and we will investigate.

Things to Look Out For

Logisim's Combinational Analysis Feature

Logisim offers some functionality for automating circuit implementation given a truth table, or vice versa. Though not disallowed (enforcing such a requirement is impractical), use of this feature is discouraged. Remember that you will not be allowed to have a laptop running Logisim on the final.

Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission


Once you've implemented your processor, you can test its correctness by writing programs to run on it! First, try this simple program as a sanity check: halt.s. This program loads the same immediate into two different registers using lui/ori and then branches back one instruction (offset = -1) if these registers are equal.

         Assembly:              Binary:
         ========               ======
         lui $r0, 0x33          2033
         ori $r0, $r0, 0x44     3044
         lui $r1, 0x33          2133
         ori $r1, $r1, 0x44     3544
   self: beq $r0, $r1, self     91FF

For practice, verify that the assembly on the left matches the translated binary on the right. This program effectively "halts" the processor by putting it into an infinite loop, so you can observe the outputs as well as memory and register state. Of course, you could do this "halt" with only the beq line, but it is very important that you test your lui/ori or the programs we will use during grading will not work.

To test your processor, open the cpu-harness.circ. Find the Instruction Memory ROM and right click --> Load Image... Select the assembled program (.hex file - see details on the Assembler below) to load it and then start clock ticks.

As described in the Deliverables, you are REQUIRED to write and submit three sample programs to test your processor (mult.s, octal.s, and multsimd.s), but you should also write others to test all your instructions.

Remember: Debugging Sucks. Testing Rocks.

We have provided an autograder with a strict subset of the tests that we will run on your processor. Passing all of our tests is not a guarantee that your processor is bug-free.


We've provided a basic assembler to make writing your programs easier so you can use assembly instead of machine code. You should try writing a few by hand before using this, mainly because it's good practice and makes you feel cooler. This supports all of the instructions for your processor.

The assembler is included in the start kit (~cs61c/proj4StartKit) or can be downloaded from the link above. The standard assembler is a work in progress, so please report bugs to Piazza!

The assembler takes files of the following form (this is halt.s, which is included in the start kit):

      lui $r0, 51
      ori $r0, $r0, 68
      lui $r1, 51
      ori $r1, $r1, 68
self: beq $r0, $r1, self

Anywhere a register is required, it must be either $r0, $r1, $r2, or $r3. Commas are optional but the '$' is not. '#' starts a comment. The assembler can be invoked with the following command:

   $ python input.s [-o output.hex]

The output file is input.hex if not explicitly set - that is, the same name as the input file but with a .hex extension. Use the -o option to change the output file name arbitrarily.

Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission


You must submit the following files:


We will be using our own versions of the *-harness.circ files, so you do not need to submit those. In addition, you should not depend on any changes you make to those files.

You must also submit any .circ files that you use in your solution (they are not copied into your .circ file when you import them, only referenced). Make sure you submit every .circ file that is part of your project! You might want to test your cpu.circ file on the lab machines before you submit it, to make sure you got everything.

From the directory containing your project files, submit using the following command:

   % submit proj4

Remember that if submit fails, your assignment has not been submitted. If submit does not ask you to confirm submitting a particular file, that file has not been submitted. If we cannot make sense of your submission, there is nothing we can do. Sorry.

Note: We will not be using git for this assignment, you will simply submit from your class account using the submit command as demonstarted above.


This project will be graded in large part by an autograder. Readers will also glance at your circuits. If some of your tests fail the readers will look to see if there is a simple wiring problem. If they can find one they will give you the new score from the autograder minus a deduction based on the severity of the wiring problem. For this reason and as neatness is a small part of your grade please try to make your circuits neat and readable.

As noted above, failure to submit files will incur massive penalties on top of the late penalty so you want to avoid this at all costs.

Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission