CS61C Spring 2012
Due Sunday, April 15th, 2012 at 11:59 PM
TA in charge: Ian Vonseggern
Full project specs can be found here.
Project Requirements
- You must implement a two-cycle design, with the stages of Instruction Fetch and Execute. You must solve control hazards by killing the instruction after the branch, and you must kill the instruction after the taken branch or jump. If the branch is not taken you must not kill it (do not kill untaken branches).
- We will test and grade your submitted Regfile.circ, alu.circ, and cpu.circ using our own harness files, meaning that your input/output pin layouts must match that of the harnesses (you do not submit the harnesses).
- Your Data Memory and Display Bundles will not be tested individually, but you must properly implement them to get full credit for your processor. You must include at least two Display Bundles (sets of 4 hex digit displays) in the main processor circuit (main of cpu.circ). Anything else can go in subcircuits. Feel free to add additional displays if it does not clutter your processor.
- We will be testing your processor's ability to handle ALL of the instructions outlined in the Instruction Set Architecture (remember, no shifting more than 15). Remember that you can test your processor by using the provided assemblers to generate instructions for your circuit. You should do this in addition to running the provided test cases.
- Make sure to submit any other .circ files that you use in your project (they are not copied into your main cpu.circ file when you import them, only referenced). You might want to test your .circ file on the lab machines before you submit it, to make sure you got everything.
- A portion of your grade will be based on tidyness and readability (i.e. labeling, neat wiring) of your Logisim files. See the Project Tips section below for some suggestions.
- Do NOT gate the clock! This is very bad design practice when making real circuits, so we will discourage you from doing this by heavily penalizing your project if you gate your clock.
Key Differences From MIPS
- The zero register isn't special. $r0 is just a regular register like $r1. (This means that addi $r1, $r0, $r0 does NOT ALWAYS set $r1 to zero!)
- Memory is addressed every 16 bits, or a WORD in our 16-bit architecture. That means each location in memory holds a 16-bit value, unlike MIPS where each location holds 8 bits.
- There are only 4 registers, instead of 32.
- Data Memory and Instruction Memory are physically separate. Remember that in MIPS, we create the illusion of separate memory with two caches, but we really have only one memory.
- Branch delay slots are not exposed to software. You have to deal with them in hardware.
- jr is not an R-type instruction. This is because if it was R-type, not all R-types would map directly to an ALU operation. This is purely for your benefit.
Project Tips
- You may use any built-in Logisim library circuit components in implementing your ALU and processor.
- Use the label tool to organize your processor. In particular label the control, datapath, and display sections, but it can also be useful to label specific busses and wires (the section labels should probably be bigger than the bus/wire labels). It could make debugging a lot easier!
- Also for labeling, you can delineate sections of your circuit using unconnected wires (they show up as gray). Logisim allows you to have these without throwing errors and they won't affect your circuit.
- Tunnels are extremely handy not only for eliminating large portions of a wire, but also because you can make any arbitrary number of tunnel openings! This is handy for long wires that branch often and connect multiple blocks/sub-circuits.
- Below is an example of some of the good labeling techniques mentioned above, as applied to the pipelining exercise from Lab 12 (which you might or might not have done yet). Here, the intermediate registers can be shown either at the border of a stage (In2 & In3 Regs) or explicitly in-between (Stage 1/2 Reg). You should use whatever style suits you best, but the overall goal is tidyness and readability:
Possible Plan of Attack
These steps are provided just to help you get started if the project spec seems daunting/overwhelming. This is simply a suggested approach, so do what makes the most sense to you. For example, some of you may want to design the control before the datapath.
- Take the time to look at some of the Logisim help files: Help --> Library Reference. Knowing how to read these references will help a lot when you start trying to use modules you didn't encounter in homework or lab.
- Build the Register File. Test it thoroughly by varying the inputs to make sure it properly reads and stores when enabled.
- Design and build your ALU. Again, test it thoroughly using a variety of inputs.
- Build your Data Memory circuit following Section 3b of the Deliverables in the project spec and place it in main of cpu.circ. Make sure you understand how to read and write from this memory.
- Build a Display Bundle in main of cpu.circ. Make sure you know how it works and that it properly displays (and holds) the values for 16-bit inputs. Then copy this so that you have at least two. Place these somewhere off to the side of main for now.
- Import your Register File and ALU into cpu.circ (use Project --> Load Library --> Logisim Library...). Think about any other components you will need for a single-cycle datapath. Build these, and then lay out everything. Wire these components together so that this datapath can execute every instruction our ISA supports. Be sure to identify any control signals you will need to generate.
- Design your control (the combinational logic for all of your control signals). The recommended method is the AND logic/OR logic breakdown (see slides 23-26 of the Lecture on 11/2). Connect the control to the datapath.
- Test I- and R-format instructions individually (including loads, stores, and disp).
- Convert your single-cycle implementation to a two-cycle datapath.
- Test branching and jumping instructions individually and then try whole programs.
- Finish writing mult.s, octal.s, and multsimd.s.
- Submit your processor and programs.
- Rejoice! ... and then sleep!
Back to full project specs.