Updates
- 02/09 : Project 1 released.
- 02/17 11:34 AM : Small bug in memory.c: line that says
uint8_t *mem;
should beuint8_t *mem = NULL;
. It has been fixed in the framework code.
Clarifications/Reminders
- You'll need to be on the Orchard or hive machines to compile the test files, because they require mips-gcc and mips-ld.
- Your disassembly code for
lui
should print the immediate field in lowercase hexadecimal, with no leading 0's and with a0x
prepended. - Remember, in our program, all registers are automatically initialized to zero, even the stack pointer (
$sp
). So, when you write test code, don't assume the stack pointer is pointing at the top of memory (where the stack usually starts). - Please be careful to not make typos in your disassembly printouts, such as misspelling or forgetting the newlines.
- For instructions with sign-extended immediate fields, make sure they can be printed out as negative values (rather than very large positive values)
- The bounds for valid memory is [1,MEM_SIZE). (1 is valid, but MEM_SIZE is not)
Goals
We hope this project will enhance your C programming skills, familiarize you with some of the details of MIPS, and prepare you for what's to come later in lecture when we dive into the processor.
Background
In this project, you will create an instruction interpreter for a subset of MIPS code. You'll provide the machinery to decode and execute a couple dozen MIPS instructions. You're creating what is effectively a miniature version of MARS!
Readings
You will find the following readings useful for this project:
- P&H 2.1 to 2.10 (MIPS instructions, number and instruction representations in binary)
- K&R 6.1,6.2,6.4,6.7,6.8,6.9 (structs, unions, bitfields)
The MIPS green sheet provides information necessary for completing this project.
Getting started
This is an individual assignment; you must work alone.
Make sure you read through the project first.
Copy the files in the directory ~cs61c/proj/01
to your proj1
directory, by entering the following command:
$ mkdir ~/proj1 $ cp -r ~cs61c/proj/01/* ~/proj1
The files you will need to modify and submit are:
processor.c
: C source file which implements the processor.memory.c
: C source file which implements the memory interface.disassemble.c
: C source file which implements disassemble.
Also included are these files. You do not need to look at load_program.c
, load_program.h
, or elf.h
, but it may be helpful to look at all the other files.
sim.c
: C source file which contains the top level simulator. This file contains the main function.processor.h
: C header file for processor.memory.h
: C header file for memory.disassemble.h
: C header file for disassembler.load_program.c
: C source file which implements loading an executable file.load_program.h
: C header file for program loader.elf.h
: C header file for ELF definitions. (ELF
is the standard executable file format in Linux.)Makefile
: File which records all dependencies.mipscode/*
: Assembly and C source files for tests.
The MIPS Simulator
The files provided in the start kit comprise a
framework for a MIPS simulator. You’ll complete the program by adding code
to processor.c
and memory.c
to execute
each instruction and perform memory access. Additionally, you’ll add code to disassemble.c
to print out the human-readable disassembly
corresponding to the instruction’s machine code. Your simulator must be
able to simulate the machine code versions of the following MIPS machine instructions.
We’ve already implemented the instructions in the second table for you, so you
have an example of an R-type, I-type, and J-type instruction.
It is critical that you read and understand the definitions in processor.h
before starting the project. If they look mysterious, re-read chapter 6 of K&R, which covers structs, bitfields, and unions. Check yourself: why does sizeof(inst_t) == 4?
INSTRUCTION |
TYPE |
OPCODE |
FUNCT |
OPERATION |
sll rd,rt,shamt |
R |
0x0 |
0x0 |
R[rd] <- R[rt] << shamt |
srl rd,rt,shamt |
R |
0x0 |
0x2 |
R[rd] <- R[rt] >> shamt |
sra rd,rt,shamt |
R |
0x0 |
0x3 |
R[rd] <- (signed)R[rt] >> shamt |
jr rs |
R |
0x0 |
0x8 |
PC <- R[rs] |
jalr rd,rs |
R |
0x0 |
0x9 |
tmp <- PC + 4 PC <- R[rs] R[rd] <- tmp |
mfhi rd |
R |
0x0 |
0x10 |
R[rd] <- RHI |
mflo rd |
R |
0x0 |
0x12 |
R[rd] <- RLO |
mult rs,rt |
R |
0x0 |
0x18 |
RLO <- {lower 32 bits of R[rs] * R[rt]} |
addu rd,rs,rt |
R |
0x0 |
0x21 |
R[rd] <- R[rs] + R[rt] |
subu rd,rs,rt |
R |
0x0 |
0x23 |
R[rd] <- R[rs] - R[rt] |
and rd,rs,rt |
R |
0x0 |
0x24 |
R[rd] <- R[rs] & R[rt] |
xor rd,rs,rt |
R |
0x0 |
0x26 |
R[rd] <- R[rs] ^ R[rt] |
nor rd,rs,rt |
R |
0x0 |
0x27 |
R[rd] <- ~(R[rs] | R[rt]) |
slt rd,rs,rt |
R |
0x0 |
0x2a |
R[rd] <- (signed)R[rs] < (signed)R[rt] |
sltu rd,rs,rt |
R |
0x0 |
0x2b |
R[rd] <- R[rs] < R[rt] |
jal target |
J |
0x3 |
- |
R[31] <- PC + 4 PC <- {(upper 4 bits of PC+4), address*4} |
beq rs,rt,offset |
I |
0x4 |
- |
if(R[rs] == R[rt]) PC <- PC + 4 + signext(offset)*4 |
bne rs,rt,offset |
I |
0x5 |
- |
if(R[rs] != R[rt])
PC <- PC + 4 + signext(offset)*4 |
addiu rt,rs,imm |
I |
0x9 |
- |
R[rt] <- R[rs] + signext(imm) |
slti rt,rs,imm |
I |
0xa |
- |
R[rt] <- (signed)R[rs] < signext(imm) |
sltiu rt,rs,imm |
I |
0xb |
- |
R[rt] <- R[rs] < signext(imm) |
andi rt,rs,imm |
I |
0xc |
- |
R[rt] <- R[rs] & zeroext(imm) |
xori rt,rs,imm |
I |
0xe |
- |
R[rt] <- R[rs] ^ zeroext(imm) |
lui rt,imm |
I |
0xf |
- |
R[rt] <- imm << 16 |
lb rt,offset(rs) |
I |
0x20 |
- |
R[rt] <- signext(LoadMem(R[rs]+signext(offset), byte)) |
lw rt,offset(rs) |
I |
0x23 |
- |
R[rt] <- LoadMem(R[rs]+signext(offset), word) |
lbu rt,offset(rs) |
I |
0x24 |
- |
R[rt] <- zeroext(LoadMem(R[rs]+signext(offset), byte)) |
sb rt,offset(rs) |
I |
0x28 |
- |
StoreMem(R[rs]+signext(offset), byte, R[rt]) |
sw rt,offset(rs) |
I |
0x2b |
- |
StoreMem(R[rs]+signext(offset), word, R[rt]) |
The following instructions have already been implemented for you.
INSTRUCTION |
TYPE |
OPCODE |
FUNCT |
OPERATION |
syscall |
R |
0x0 |
0xc |
(perform system call) |
or rd,rs,rt |
R |
0x0 |
0x25 |
R[rd] <- R[rs] | R[rt] |
j target |
J |
0x2 |
- |
PC <- {(upper 4 bits of PC+4), address*4} |
ori rt,rs,imm |
I |
0xd |
- |
R[rt] <- R[rs] | zeroext(imm) |
If you have any questions about the semantics of the instructions, consult P&H (4th ed.) Section 2.9 and Appendix B, particularly if you find our pseudocode for loads and stores to be confusing. (The first argument to LoadMem and StoreMem in our pseudocode is the memory address. The second argument to both LoadMem and StoreMem is the width of the access. The third argument to StoreMem is the store data.)
The MIPS system you’re implementing is little-endian. Look at P&H (4th edition) page B-43 for further information on endianness (byte order). We chose little endian because the host machines are little endian, and this avoids some complexity for sub-word loads and stores.
In our variant of MIPS, beq and bne are not delayed branches. (If you don’t know what that means, just ignore it; your default assumption about the behavior of branches is probably correct for this project. We’ll talk about this topic later in the semester.)
Initially, you will be able to run a program called “simple”, which only uses the instructions we implemented for you, by running the following commands:$ cd ~/proj1 $ make $ ./mips-sim mipscode/simple Hello, world! exiting the simulator
The Framework Code
The framework code we’ve provided begins by doing the following.
- It reads the executable program binary, whose filename is specified on the command line, into the simulated memory, starting at address 0x00001000.
- It initializes all 32 MIPS registers to 0 and sets the program counter (PC) to 0x00001000.
- It sets flags that govern how the program interacts with the user. Depending on the options specified on the command line, the simulator will either show a dissassembly dump of the program on the command line, or it will execute the program.
It then enters the main simulation loop, which simply
calls execute_one_inst()
repeatedly until the simulation is complete.
execute_one_inst()
performs the following tasks:
- It fetches an instruction from memory, using the PC as the address.
- It examines the opcode to determine what instruction was fetched.
- It executes the instruction and updates the PC.
The framework supports a handful of command-line options:
-i
runs the simulator in “interactive mode,” in which the simulator executes an instruction each time the Enter key is pressed. The disassembly of each executed instruction is printed.-t
runs the simulator in “tracing mode,” in which each instruction executed is printed.-r
instructs the simulator to print the contents of all 32 registers after each instruction is executed. It’s most useful when combined with the -i flag.-d
instructs the simulator to disassemble the entire program, then quit.
Your Job
Your job is to complete the implementations of
the disassemble()
function in
disassemble.c
, the execute_one_inst()
function in processor.c
, and the load_mem(), store_mem(), access_ok()
functions in memory.c. Right now, they only operate correctly
for the or, ori, j,
and syscall instructions. By the
time you’re finished, they should handle all of the instructions in the table
above.
Part 1 (Due 2/17): Your first task will be to implement the disassembler. (25 pts)
- Print the instruction name. If the instruction has arguments, print a tab (\t).
- Print all arguments, following the order and
formatting given in the INSTRUCTION column of the table above.
- Arguments are generally comma-separated (lw/sw, however, also use parentheses), but are not separated by spaces.
- Register arguments are printed as a $ followed by the register number, in decimal (e.g. $0 or $31).
- Zero-extended immedates (e.g. for ori) are printed as lowercase hexadecimal numbers with a leading 0x but without extra leading zeros (e.g. 0x0 or 0xffff).
- Jump addresses should be printed like zero-extended immediates, but multiplied by 4 first. (Assume the upper 4 bits of PC+4 are zero.)
- Sign-extended immediates (e.g. for addiu, sw, or beq) are printed as signed decimal numbers (e.g. -12 or 48). For branch offsets, multiply the offset by 4.
- Shift amounts (e.g. for sll) are printed as unsigned decimal numbers (e.g. 0 to 31).
- Print a newline (
\n
) at the end of an instruction. - We will be using an autograder to grade this task. If your output differs from ours due to formatting errors, you will not receive credit.
- We have provided a disassembly test for you. Since a test is only covering a subset of possible scenarios, however, passing this test does not mean that your code is bug free. You should identify the corner cases and test them yourself.
Run the disassembly test by typing in
“make disasmtest
”. If
your disassembly matches the output, you will get a “DISASSEMBLY TEST PASSED!” message.
$ cd ~/proj1 $ make disasmtest ./mips-sim -d mipscode/insts > insts.dump DISASSEMBLY TEST PASSED!
If your disassembly does not match the output, you will
get the difference between the reference output and your output, and a
“DISASSEMBLY TEST FAILED!” message. Make sure you at least pass this test before submitting disassemble.c
$ cd ~/proj1 $ make disasmtest ./mips-sim -d mipscode/insts > insts.dump 56c56 < 000010dc: addiu $30,$0,11 --- > 000010dc: addiu $30,$0,0x11 66c66 < 00001104: bne $4,$5,44 --- > 00001104: bne $4,$5, 44 DISASSEMBLY TEST FAILED!
For this part, only changes to the files disassemble.c
will be considered by the autograder.
To submit, enter in the commands:
$ cd ~/proj1 $ submit proj1-1
Part 2 (Due 2/24): Your second task will be to actually implement the remaining instructions in the processor. (75 points)
One issue we have not addressed thus far is address alignment for loads and stores. The simulator should abort if a memory access is improperly aligned or outside of the range [1,MEM_SIZE). The same behavior should occur for misaligned loads and stores. lw and sw require 4-byte alignment, like the PC, and lb, lbu, and sb are always properly aligned. For misaligned or out-of-range addresses (this includes the NULL address 0), you must have access_ok() return 0 in memory.c, which will cause the simulator to print an error message and abort. This is analogous to the segmentation fault you may see when an x86 program does an illegal memory access.
mult
should split the upper and lower 32 bits of the 64 bit result. To do this we have provided you with the function perform_mult
which takes two registers as the source, and pointers to two destination registers.
We have provided a simple self-checking assembly test that tests several of the instructions. However, the test is not exhaustive and does not exercise every instruction. Here’s how to run the test. (The output is from a working processor.)
$ cd ~/proj1 $ make runtest ./mips-sim -r mipscode/insts > test.trace insts_test PASSED ./mips-sim -r mipscode/rt3 > test.trace rt3_test PASSED ./mips-sim -r mipscode/rt13 > test.trace rt13_test PASSED ./mips-sim -r mipscode/rt25 > test.trace rt25_test PASSED Tests Complete
Most likely you will have bugs, so try the tracing mode or other debugging modes described in the Framework code section above.
$ ./mips-sim -t mipscode/simple
00001000: ori $4,$4,0x1014
00001004: ori $2,$0,0x4
00001008: syscall
Hello, world!
0000100c: ori $2,$0,0xa
00001010: syscall
exiting the simulator
We have provided a few more tests and the ability to write your own. We described simple above, which prints out “Hello, world!”, and is written in assembly. Here’s an example of how to add an assembly test:
- Create the new assembly file in the mipscode directory. (Use mipscode/simple.s as a template.) Let’s assume your test is in mipscode/foo.s.
- Add the base name of the test to the list of ASM_TESTS in the Makefile. To do this, just add foo to the end of line 4.
Now build your assembly test, and then run it by typing in the following commands:
$ cd ~/proj1 $ make $ ./mips-sim mipscode/foo
You can, and indeed should, write your own assembly tests to test specific instructions and their corner cases. Furthermore, you should be compiling and testing your code after each group of instructions you implement. It will be very hard to debug your project if you wait until the end to test.
For the final results, only changes to the files disassemble.c
, processor.c
, and memory.c
will be considered by the autograder.
To submit, enter in the commands:
$ cd ~/proj1 $ submit proj1-2