Project 2: Processor Design - Abridged Notes

CS61C Spring 2015

Due Sunday, March 24th, 2015 at 11:59 PM

TAs in charge: Fred Hong and William Huang

Full project specs can be found here.

Project Requirements

• You must implement a two-cycle design, with the stages of Instruction Fetch and Execute. You must solve control hazards by killing the instruction after the branch, and you must kill the instruction after the taken branch or jump. If the branch is not taken you must not kill it (do not kill untaken branches).
• We will test and grade your submitted regfile.circ, alu.circ, mem.circ, and cpu.circ using our own harness files, meaning that your input/output pin layouts must match that of the harnesses (you do not submit the harnesses).
• We will be testing your processor's ability to handle ALL of the instructions outlined in the Instruction Set Architecture (remember, no shifting more than 31). For part 1, you can run the provided short-test.sh to start the sample autograder tests for alu.circ and regfile.circ. For part 2, you can test your processor by using an assembler to generate some instructions and more sample tests, all of which we will provide with the release of proj2-2.
• Make sure to submit any other .circ files that you use in your project (they are not copied into your main cpu.circ file when you import them, only referenced). You might want to test your .circ file on the lab machines before you submit it, to make sure you got everything.
• A portion of your grade will be based on tidyness and readability (i.e. labeling, neat wiring) of your Logisim files. See the Project Tips section below for some suggestions.
• Do NOT gate the clock! This is very bad design practice when making real circuits, so we will discourage you from doing this by heavily penalizing your project if you gate your clock.

Key Differences From MIPS

1. Memory is addressed every 32 bits, or a WORD in our 32-bit architecture. That means each location in memory holds a 32-bit value, unlike MIPS where each location holds 8 bits.
2. RAM and ROM modules in Logisim are addressed with 24-bits, which means that there will be some loss of information when converting from the 32-bit addresses used in MIPS instructions. That is okay, but make sure you know what is being byte- or word-addressed.
3. Be very careful when dealing with absolute addresses, whether it's for jumping or for accessing data memory. The instructions you will be running will assume that their addresses begin at standard locations, such as the default memory configuration in MARS. That is, .text begins at 0x00400000 and .data begins at 0x10010000, both of which are byte-addressed. In your processor, however, both instruction and data memory start at 0x000000.
4. You will only implement 4 registers, instead of all 32. This means you have to route register requests to either run.circ or regfile.circ, depending on which registers are being accessed.
5. Data Memory and Instruction Memory are physically separate. Remember that in MIPS, we create the illusion of separate memory with two caches, but we really have only one memory.
6. Branch delay slots are not exposed to software. You have to deal with them in hardware.
7. jr is not an R-type instruction. This is because if it was R-type, not all R-types would map directly to an ALU operation. This is purely for your benefit.
8. There are two new R-type instructions for you to implement, bitpal and lfsr.

Project Tips

• You may use any built-in Logisim library circuit components in implementing your ALU and processor.
• Use the label tool to organize your processor. In particular label the control, datapath, and display sections, but it can also be useful to label specific busses and wires (the section labels should probably be bigger than the bus/wire labels). It could make debugging a lot easier!
• Also for labeling, you can delineate sections of your circuit using unconnected wires (they show up as gray). Logisim allows you to have these without throwing errors and they won't affect your circuit.
• Tunnels are extremely handy not only for eliminating large portions of a wire, but also because you can make any arbitrary number of tunnel openings! This is handy for long wires that branch often and connect multiple blocks/sub-circuits.

Possible Plan of Attack

These steps are provided just to help you get started if the project spec seems daunting/overwhelming. This is simply a suggested approach, so do what makes the most sense to you. For example, some of you may want to design the control before the datapath. Also, throughout this process, test liberally with the sample autograder tests and ones that you make yourselves.

1. Take the time to look at some of the Logisim help files: Help --> Library Reference. Knowing how to read these references will help a lot when you start trying to use modules you didn't encounter in homework or lab.
2. Build the Register File. Test it thoroughly by varying the inputs to make sure it properly reads and stores when enabled.
3. Design and build your ALU. Again, test it thoroughly using a variety of inputs.
4. Review your understanding of addressing, ie byte- vs word-, how instructions encode addressing information, where the data is located in memory as a whole. Addressing can become a major hurdle in this project if you don't understand it well.
5. Build your Data Memory circuit following Section 5 of the Deliverables in the project spec. Make sure you understand how to read and write from this memory.
6. Open up cpu.circ and look at the layout. Think about any other components you will need for a single-cycle datapath. Build these, and then lay out everything. Wire these components together so that this datapath can execute every instruction our ISA supports. Be sure to identify any control signals you will need to generate.
7. Design your control (the combinational logic for all of your control signals). The recommended method is the AND logic/OR logic breakdown. Connect the control to the datapath.
8. Test I- and R-format instructions individually (including loads and stores).
9. Convert your single-cycle implementation to a two-cycle datapath.
10. Test branching and jumping instructions individually and then try whole programs.
11. Finish writing the test programs in section 6 of deliverables. These will be released with proj2-2.
12. Submit your processor and programs.
13. Rejoice! ... and then sleep.

Back to full project specs.