University of California at Berkeley
College of Engineering
Department of Electrical Engineering and Computer Science

CS61C, Summer 2008

HW 5: ALU in Logisim

Staff in charge: Albert Chae

Due Tuesday, July 29, 2008 @ 11:59:59pm



ALU-spec.png

In this assignment, you will implement a 16 bit ALU in logisim with the following inputs and outputs.

Wire name Direction Bit Width
InputA input 16
InputB input 16
Select input 3
Result output 16
Signed Overflow output 1
Unsigned Overflow output 1
Equals output 1

Functions

The nine functions that you will implement are: add, subtract, OR, AND, shift left logical, shift right logical, shift right arithmetic, set less than, and EQUAL. The ALU will perform the desired function on two 16-bit inputs (X and Y, where x0 is the lowest order bit for x, y0 is the lowest order bit for y, etc...) and output the result on the 16-bit Result bus. The function will be determined by the value of a control signal (Select), as listed below.

In addition to the 16 bits of output produced in Result, three additional outputs will be produced: unsigned overflow, signed overflow and equals.

For the shift instructions detailed below (sll, srl, sra), the shift amount is ONLY the least 4 significant bits of Y. You can ignore the other bits of Y.

Here's what occurs for each operation:

Select op Result
000 or X | Y
001 and X & Y
010 add X + Y (and signal if either overflow occurs)
011 sub X - Y (and signal if signed overflow occurs)
100 sll X << Y (logically, don't sign extend!)
101 srl X >> Y (logically, don't sign extend!)
110 sra X >> Y (arithmetically, do sign extend!)
111 slt if (X < Y) //Treat X and Y as SIGNED!
then result = 1
else result = 0
XXX eq X == Y (Have this value be on the equals output regardless of selection)

Testing

Think about intuitive ways to test your ALU. If the grader can look at your logisim file and quickly see that everything is in working order, it will be to your advantage. You might consider some method for automatically testing your ALU, such as a counter. Perhaps you should add testing logic that signals an error if an incorrect value is seen. Think about this; we want to see some form of testing suite in your outer-most circuit design. This is also good practice for building tests for proj3.

README

You will need to submit a README file with this assignment. This should include any instructions on running your circuit (and any testing suite you choose to implement) and any particular quirks of design or behavior you feel the graders should know about.

Not Allowed In This Assignment

You may only use tools from the "Base" and "Gates" libraries in Logisim. Do not use any items from the Memory, Plexers, Arithmetic, or Legacy libraries. Any ALU pieces built using any of these illegal components will be given no credit.

Details & Hints

Submission Details

Create a directory named 'hw5' containing a README, alu.circ, and any additional files needed for your submission. While in that directory, run 'submit hw5'. If you included an image, make sure to say "yes" when the submit script prompts you about it.

Credits

Thanks to former TA Ben Sussman and others for the original spec and the cool ALU diagram.