Current time: Tue Mar 19 01:14:25 2024
Deadline: Wed Jul 30 23:59:00 2008
Why does it make it easier to design with flip-flops if the hold time is less than the clk-to-q delay?
Why is it harder to go from a truth table to a gate level description? Not impossible, just harder.
How would you extend the design on p.300 (of P & H) to handle J-Type instructions? Do not worry about the control, or drawing a schematic. Just generally what blocks/wires would you need to add where.