Fall 2001
Schedule (Version Date 2/10/00)
A.R.
Neureuther
WEEK LECTURE TOPICS READING LAB
1.
1/17 overview; circuits from E40 HS
Ch 1
2.
1/19 Amplification gain, Rin, Rout, equivalent circuits HS 8.4
Week 2 General Circuits, Basis Silicon
Physics, Fabrications Exp 1
3.
1/22 Two-Ports, multistage HS
8.2.2, 9.1
4.1/24
Basic silicon physics HS
2.1-2.4, 4.1.1, 4.5.7, 6.2, 7.1.1, 7.7
5
1/26 IC resistors HS
2.5.4-2.6
Week 3 Junction
and MOS Capacitance Exp 2
6. 1/29 Electrostatic analysis for distributed
charge density HS 3.1
7.
1/31 pn junction capacitance HS
3.2,3.3,3.6
8.
2/2 MOS threshold voltage HS
3.7
Note: HW 4.1 is a one-sided version of the material in 3.4-3.5.
The contact potential in 3.4.3 was simplified to assuming metal can be treated as n+ doping.
Week 4 MOS I versus V Models Exp 3
9.
2/5 I versus V basic HS
4.1-4.3
10.
2/7 2nd order effects HS
4.4
11.
2/9 Small signal model HS
4.5-4.5.3
Week 5 Complete MOS Model Exp 4
12.
2/12 NMOS two-port, PMOS model, CMOS gain HS
8.3, 4.5.6, 5.3,
13.
2/14 MOS capacitance, SPICE models HS
4.5.4, 4.5.6, 4.6
14.
2/16 Review HS
none
Week 6 Review and Phasors No Lab
H.
2/19 Holiday
15.
2/21Review, recap of phasors LM
189-210
16.
2/23 FIRST MIDTERM
Week 7 Basic Frequency Response, Diode
Physics Exp 5
17.
2/26 Circuit analysis with phasors LM
210-213
18.
2/28 Bode plots – general approach HS
10.1
19.
3/2 pn diode current HS
6.1,6.3
Week 8 Diode and Bipolar Physics Exp 7
20.
3/5 pn diode model including small signal HS
6.4,6.9
21.
3/7 Bipolar transistor physics HS
7.1-7.3
22.
3/9 Bipolar transistor model (Ebers Moll and s.s.) HS 7.4-7.5
Week 9 pnp Bipolars Transistors, Basic BJT Circuits Lab Quiz, Exp 6
23.
3/12 pnp, SPICE, basic circuits HS
7.7-7.8
24.
3/14 CE amplifier - large and small
signal HS
8.1-8.4
25.
3/16 CE amplifier – frequency response HS
10.31
Week 10 Review and Integration No Lab
26
3/19 Examples and physical parameters recap
HS, LM
27.
3/21Review (none)
28.
3/23 SECOND MIDTERM
Week 11 Amplifier Configurations Exp 8
29.
4/2 Common source and emitter HS
8.5-8.6
30.
4/4Emitter degeneration and common base/gate HS
8.7-8.8
31.
4/6 Common collector/drain HS
8.9
Week 12 Amplifier Configurations and
Multistage Circuits Exp 10
32.
4/9 Summary of configurations recap
HS 8
33.
4/11 Multistage and small signal HS 9.1-9.2
34.
4/13 Direct-coupled amplifiers HS
9.3
Week 13 Advanced Multistage Amplifiers Exp 11
35.
4/16 DC voltage and current sources HS
9.4
36.
4/18 Two-stage and BiCMOS example HS
9.5-9.6
37.
4/20 Frequency response – current amplifier HS
10.3
Week 14 Frequency Response Exp 9
38.
4/23 Frequency response – voltage amplifier HS
10.4
39.
4/25 Frequency response – voltage buffer HS
10.5
40.
4/27 Frequency response – current buffer HS
10.6
Week 15 Frequency Response and Example Circuits Lab Quiz, Makeup
41.
4/30 Frequency response multistage HS
10.7
42.
5/2 Example circuits – recognize components Handout
43.
5/4 Example circuits – frequency response Handout
Week 16 Review No Lab
44. 5/7 Review for Final Exam
Final Exam, Group 6, 8-11 AM Monday May 14th,
location TBA
HS: R. T. Howe and C. G. Sodini, Microelectronics:
An Integrated Approach, Prentice Hall, 1997.
Reader: EE 105
course reader, available at Copy Central 2560 Bancroft Way, Reader Number 165,
$15.09.