EE244 Fall 1997 Course Outline Below is a list of topics to be covered and an approximate order. The exact material and emphasis will be determined by student interests and needs as the course progresses. All preliminary examination material will be covered in detail. Electronic Systems Design Overall Principles
Physical Design Styles and Evolution Full Custom Design, Cell-based Design, Structured Custom Design
FPGA Impact of Deep Sub-Micron Technologies Communication-based Design Computational Issues in Physical Design General Issues, Solution time, Problem size Data Structures for Physical Design Role of Computational Geometry
Representing geometry & its characteristics Representing the plane: Grids, tessellation, etc.
Bins and Trees
Corner-stitching
Overall characteristics Representing Connectivity Abstracting cells
Physical connectivity
Logical connectivity & Netlists
Integrating with physical information Cell-based Design Metrics for Physical Design: Distance, Connectivity, Net length, Density, Delay (net, path), Power Dissipation Interconnect Analysis Models for physical design RC Modeling
Elmore Time Constant
Penfield-Rubinstein approach
AWE
Power Dissipation Statistical Characteristics Of Wiring Rent's Rule, Donath & Heller
Power Dissipation Approximations Partitioning General problem
Quality metrics & constraints
Approaches Greedy, Kernighan-Lin, Fiduccia-Mattheyses, Stochastic approaches
Modern approaches and new directions Floorplanning What is floorplanning?
Approaches Tutte's approach, Clustering, Analytical, Simulated annealing Component Placement or Assignment What is the placement problem? Placement vs. Assignment
Complexity
Placement quality and constraints Approaches Partition-based, Min-cut, Force-directed approaches, Quadratic assignment, Simulated Annealing Routing Global routing Problem definition & classification of approaches
Routing region definition and ordering
Breadth-first search (maze), Soukup's modification, Steiner-tree-based algorithms, Integer linear programming, Simulated annealing Detailed routing Problem definition: layers, vias, etc.
Generalized routing: Grid-based, "Gridless"
Channel routing: Greedy, LEA, Yoshimura-Kuh, Dogleg, YACR2
Switchbox, Rip-up & re-route
Timing-driven routing
Cleanup & compaction Symbolic Layout Representation
Compaction 1-D Approaches, Zone Refining, 2-D Compaction Module Generation and Silicon Compilation Introduction to Layout Styles Datapath generation, parameterized layout, Weinberger Arrays & Gate Matrix, SLA's
PLA folding: Simple and Constrained
Synthetic library generation
CMOS static cell generation Transistor Sizing TILOS approach, Lagrangian Multiplier Approaches, Marple's approach, Convex programming approach Detailed Layout Analysis and Verification Circuit extraction
Solving for IR-drops, clock skew, etc.
Hierarchical layout analysis
Incremental layout analysis
Netlist comparison: Graph matching Combinatorial Complexity and General Search Computational complexity
Layout of graphs
Layout subproblems
Generalized search, rational search Utility, Branch and Bound, Probabilistic Branch and Bound, Other approaches Summary Advanced Techniques Bayesnets, more to come! Summary

 

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