EE244 Project Ideas

Noise Analysis

Shepard [ICCAD96] has proposed a method for noise integrity evaluation in complex digital circuits by generating a noise graph associated with the propagation potential of noise through pass transistor logic, as well as static and dynamic gates.  In this approach, a static worst-case noise signal is propagated through the graph and the error induced in any of the latches in the circuit is evaluated if the noise instability condition is reached.
There are a number of drawbacks in this method.  First, experience shows that the most critical noise effects, i.e. the destructive ones, are local (ranges of one or two gates) and do not originate from remote noise signals. Second, a number of sources such as the input, output, Vdd, Vss, substrate, etc. act together in a complex pattern to produce output noise. For example, noise injected at Vdd will be highly attenuated when the input is low or high and propagated when the input is in a metastable state.  Third, noise is propagated only through pass gates, which are generally followed by latches, hence not further propagated.  We propose to develop a graph propagation technique which applies to settling time as opposed to noise signals. Settling time variations can be efficiently propagated through gates and latches and the resulting errors can be appropriately evaluated everywhere in the circuit.  Settling time can be compactly formulated as a function of local variables, such as cross-talk, supply ripple or glitches using, for example, SPICE. This approach eliminates most of over- or under-estimations and enables the user to better understand the real effects of noise and cross-talk during all design phases.
This work consists of the following tasks:
1. construct a settling time model based on random input vectors
2. evaluate total settling time in macros using a graph search
3. compute input vectors for each macro based on wire delay and settling times
The final algorithm will iterate 1. 2. and 3. until consistency is reached.

Active IP Watermarking

Employing well-known techniques, it is possible today to reverse-engineer virtually any IC design, given a sufficient pool of samples and enough time. Developing techniques for direct Intellectual Property (IP) protection, if ever possible, is impractical and very expensive.
Recently, a new IP protection paradigm has been proposed based on a technique known as watermarking. Watermarking, applied to hard IPs, consists in embedding a coded signature within the intrinsic structure of the IP.  Watermarking, to be effective, needs be (a) unique and highly resilient; (b) hard to detect, counterfeit or remove; (c) easy to verify.  In addition, the procedure needs be transparent to the user and cheap, and have little or no impact on performance.  In this research we propose to use such unique features as the constraints on performance and signal interface and the topology of signal, power and clock interconnections to encrypt the signature.  Resilience is ensured by the highly redundant character of the signature and the different types of encryption used for each feature encoding.  Low hardware overhead is guaranteed, provided that the layout solution has a large number of nearly-equivalent configuration, which is always the case in complex IPs such as the ones we want to protect. We will prove how detecting and forging a signature can be made arbitrarily hard, while the procedure can be easily introduced in a large number of existing optimization algorithms, normally used in physical design.

Passive IP Watermarking

An alternative watermarking technique, involving no encoding into the IP, consists of using substrate injection signatures as a fingerprint for a particular logic circuit given a specific set of input vector sequence. A spectral estimation technique based on the Burg method is then used to discriminate the signature in a noisy environment, i.e. where other noise injecting circuits are operating simultaneously.  The proposed method is useful since it allows to detect the presence of a certain IP in a circuit without re-design, or any modifications to the chip being tested. The signature characterization could prove useful also for detection of malfunctions and to pinpoint the exact source of the problem.

NexSis and Layout Generation

In this project we propose the definition of a syntax for compact representation of modules and interconnect areas to be efficiently generated in Cadence’s layout environment. The assignment also includes the development of a general module generator for modules and interconnect with fixed internal floorplanning to be integrated in the NexSis environment.