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Electrical Engineering and Computer Sciences Department
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EE249, Fall 2007
Design of Embedded Systems: Models, Validation and Synthesis

Tues. and Thurs.: 11:00 - 12:30 pm, also,
Tues.: 5:00 - 6:00 pm and Thurs.: 4:00 - 6:00 pm
521 Cory Hall


Prerequisite:  There is no pre-requisite for this course, but some exposure to the basics of real-time embedded system and an inclination to formal reasoning is welcome.


  • No textbook required for this course.

  • Course Flier

  • Academic Dishonesty Policy
  • Lecturer:
    Professor Alberto L. Sangiovanni-Vincentelli
    515 Cory Hall
    Phone: (510) 642-4425
    alberto@eecs.berkeley.edu

    Office Hours:
    Tues. and Thurs.: 12:30 -1:30 pm,
    515 Cory Hall

    Assistant:
    Alessandro Pinto
    apinto@eecs.berkeley.edu

    Teaching Assistant:
    Qi Zhu
    zhuqi@eecs.berkeley.edu

    Qi Zhu's Office Hours:
    Tues.: 3:00 - 5:00 pm,
    545P Cory Hall

    Course Administrative Assistant:
    Therese George
    253 Cory Hall
    (510) 642-2384
    therese@eecs.berkeley.edu


    Welcome to EE249

    This class presents approaches to the new system science based on theories, methods and tools that were in part developed at the Berkeley Center for Hybrid and Embedded Software Systems (CHESS) and the Giga-scale System Research Center (GSRC) where heterogeneity, concurrency, multiple levels of abstraction play an important role and where a set of correct-by-construction refinement techniques are introduced as a way of reducing substantially design time and errors. Real-life applications including car electronics and building automation are used to illustrate system-level design methodologies and tools.

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    Announcements:

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    Class Organization:

  • Part 1: Introduction
  • Design complexity, example of embedded systems,traditional design flow, Platform-Based Design.

  • Part 2: Functional modeling, analysis and simulation
  • Introduction to models of computation. Finite State Machines and Co-Design Finite State Machines, Kahn Process Networks, Data Flow, Petri Nets, Hybrid Systems. Unified frameworks: the Tagged Signal Model, Agent Algebra.

  • Part 3: Architecture and performance abstraction
  • Definition of architecture, examples: distributed architecture, coordination, communication. Real time operating systems, scheduling of computation and communication.

  • Part 4: Mapping
  • Definition of mapping and synthesis. Software synthesis, quasi static scheduling. Behavioral synthesis. Communication Synthesis and communication-based design.
    • Part 5: Verification
      Validation vs Simulation. Verification of hybrid system. Interface automata and assume guarantee reasoning.
  • Part 6: Applications
  • Automotive: car architecture, communication standards (CAN, FlexRay, AUTOSAR), scheduling and timing analysis.
    Building automation: Communication (BacNet, LonWorks, ZigBee). Applications to monitoring and security.

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    Lectures:

  • Introduction to EE249
  • Part 2:  Methodology PBD
  • Part 3:  Models of Computation
  • Finite State Machines

  • Statecharts

  • Data Flow

  • Overview of the Ptolemy Project

  • Extending Ptolemy II

  • Petri Nets

  • Tagged Signal Model

  • Esterel

  • Lustre

  • Model-based Software Implementation

  • Abstract Algebra

  • Software Estimation

  • Metropolis Metamodel

  • Introduction to Controller Area Network

  • Real-Time Operating Systems and Schedulability Analysis

  • Design Methods and Tools for Real-Time Embedded Systems
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    Discussions:

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    Labs & Homework:

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    Additional Reference Materials:

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    Projects:

    Below is a list of projects. The order in which they are listed does not reflect any kind of priority. You should:
    1) Select a project that you are interested in from the list below
    2) Contact the project mentor(s) and go talk to her/him/them
    3) Find a project-mate (optional) and give a name to your team (maximum 2 persons, some projects might have suggested number of students listed. You can also find your project-mate first then look for project together.)
    4) Contact your TA with the team name, team members and project title
    • Distributed code synthesis for Simulink Models:
    • Mentors: Prof. Reinhard von Hanxleden (rvh@informatik.uni-kiel.de), Stavros Tripakis (tripakis@cadence.com)
    This project is concerned with the synthesis of distributed systems from block diagrams, as found in Simulink models. Given a possibly multi-rate Simulink model and a concurrent, distributed execution platform, an implementation should be generated that adheres to the semantics of the original model.
    Assumptions:
    * The block diagram is acyclic at the top level. Cycles are allowed only if they are "broken" by unit delays.
    * Code is supposed to run on a distributed execution platform with processing nodes and a network. The network provides FIFO, lossless point-to-point communication between nodes.
    * Mapping of blocks to nodes is fixed and (at least initially) one-to-one.
    Objectives:
    * Minimal message traffic
    * Minimal latencies, maximal throughput

    In the course of the project, a prototypical implementation should be realized, which builds on Matlab/Simulink and the Real-Time Workshop, and uses a networked PCs as execution platform.

    Initial references (to be extended):
    [1] Abhijit Davare, Qi Zhu, Marco Di Natale, Claudio Pinello, Sri Kanajan, Alberto Sangiovanni-Vincentelli.  "Period Optimization for Hard Real-time Distributed Automotive Systems."  Design Automation Conference, June, 2007.  http://chess.eecs.berkeley.edu/pubs/227.html
    [2] A. Girault. "A survey of automatic distribution method for synchronous programs." In F. Maraninchi, M. Pouzet, and V. Roy, editors, International Workshop on Synchronous Languages, Applications and Programs, SLAP'05, ENTCS, Edinburgh, UK, April 2005. Elsevier Science.
    ftp://ftp.inrialpes.fr/pub/bip/pub/girault/Publications/Slap05/main.pdf

    [3] E. A. Lee and A. Sangiovanni-Vincentelli. "A framework for comparing models of computation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(12):1217-1229, 1998.
    http://ptolemy.eecs.berkeley.edu/publications/papers/98/framework/ieeeVersion.pdf

    [4] M. Zennaro and R. Sengupta. "Distributing Synchronous Programs Using Bounded Queues." 5th ACM International Conference on Embedded Software (EMSOFT'05).
    http://www.zennaro.net/papers/EMSOFT05-zennaro.pdf

    • Platform based design of distributed estimation algorithms for WSNs:
      Mentor: Carlo Fischione (fischion@EECS.Berkeley.EDU)

    • The characteristics of wireless sensor networks (WSNs) motivate the development of new classes of distributed estimation algorithms, which explore the limited power, computing and communication capabilities of these systems. Suitable cooperation between neighboring nodes improves the estimation quality considerably. The characteristics of the wireless propagation make it natural to exploit cooperative schemes for transmission. When a sensor uses readings from neighboring sensors, it can overcome intrinsic performance limitations due to uncertainty, and noise present in individual devices.
      In [1], a distributed estimation algorithm for tracking an unknown time-varying physical variable has been investigated. Such estimator for WSNs belongs to a class of recently developed filtering algorithms that explore the rich potential of performing in-network computing. By letting the network do the computations, it is possible to reach a scalable, fault tolerant and flexible design.
      The goal of the project is first to provide a platform based design of the distributed estimation algorithm in [1]. Specifically, the main components of the algorithm should be abstracted as functional blocks. Second, a protocol description of the algorithm should be done. Third, an evaluation of the computational complexity of the algorithm has to be performed in order to provide an understanding of the trade-off among communication constraints, computing efforts and estimation quality. Time permitting, the implementation of the algorithm with a simulation environment or on a real sensor network test bed would be desirable.

      [1] A. Speranzon, C. Fischione, K. H. Johansson, “A Distributed Minimum Variance Estimator for Wireless Sensor Networks”, submitted, available online at
      http://www.eecs.berkeley.edu/~fischion/Publications/TRITA-EE_2006_031.pdf
      [2] F. Graziosi, F. Santucci and S. Tennina, “Location service design with a platform based approach in ad-hoc wireless sensor networks”, IEEE Globecom, 2004.
      [3] A. Pinto, A. Bonivento, A. L. Sangiovanni-Vincentelli, R. Passerone and M. Sgroi, “System level design paradigms: Platform-based design and communication synthesis”, ACM Trans. Des. Autom. Electron. Syst. vol. 11, no. 3, pp. 537 -- 563, 2006.
    • Design of transmit rate and radio frequency power control algorithms with low computational complexity for WSNs:
    • Mentor: Carlo Fischione (fischion@EECS.Berkeley.EDU)

      The design of efficient power control algorithms for wireless sensor networks (WSNs) is crucial to reduce energy consumption to a level suitable for many applications. When recharging of the sensors is not possible, radio power control is very important in order to increase the network lifetime. Transmission power is responsible for up to 70% of the total energy consumption for off-the-shelf sensor nodes. Keeping the transmit power under control is furthermore beneficial to reduce the packet collision probability, which otherwise leads to more retransmitted packets wasting even more energy.
      In [1] an effective power control strategy to achieve maximum data rate for CDMA wireless system has been investigated. The approach was intended for third and fourth generation wireless systems, and is based on the solution of a mixed integer-real combinatorial optimization problem. However, such systems are usually equipped with large processing capabilities. Off-the-shelf popular sensor networks, as the Telos, make use of DS CDMA to access the wireless channel. Since they have reduced computational resources, sub-optimal solutions should be investigated.
      The goal of this research project is to provide a characterization and modeling of a sub-optimal solution for the power and transmission maximization problem for wireless sensor networks. The modeling should abstract the characteristics of the physical layer of the wireless communication channel, but at the same time the abstraction should not be too accurate in order to provide the solution of an optimization problem amenable for implementation over existing WSNs. Performance of the power control algorithms should be evaluated through computer simulations.

      [1] C. Fischione, M. Butussi, K. H. Johannson, “Power and Rate Control with Outage Constraints in CDMA Wireless Networks”, submitted, available online at
      http://www.eecs.berkeley.edu/~fischion/Publications/IR-EE-RT_2006_016.pdf
      [2] S. Boyd, S. J. Kim, L. Vandenberghe, and A. Hassibi, “A Tutorial on Geometric Programming” Optimization and Engineering, 8(1):67-127, 2007.
    • Design of low-power Minimum-Energy-Coding transreceiver for WSNs with delay and reliability constraints:
      Mentor: Carlo Fischione (fischion@EECS.Berkeley.EDU)

      Despite the advancements in hardware and software technologies, one of the most relevant constraints to embody in the design of wireless sensor networks is the energy efficiency. The nodes are supposed to be deployed with reduced energy resources and without battery replacement. Motivating examples are found in areas such as industrial automation, environmental monitoring, and surveillance. Hence, the implementation of this technology has pushed the development of techniques, protocols, and algorithms able to cope with the scarcity of communication and computation resources of the nodes.
      Several techniques have been proposed to reduce the energy consumption of WSNs, while ensuring adequate performance. Often, cross-layer approaches are necessary in order to take into account several interacting techniques and protocols, as for example, distributed source coding and sleep discipline. In [1], minimum energy coding schemes have been considered. Indeed, these schemes are easily implementable in real wireless sensor networks, and offer potentially several benefits.
      The goal of this project is to provide a performance comparison of Minimum Energy Coding techniques in terms of reliability and delay. In [1], the analysis was carried out only in term of energy consumption and successful packet transmission. However, delay constraints in the packet delivery play a relevant role in real-time applications. A performance evaluation should be carried out first though computer simulation, and then by an implementation on a real wireless sensor test bed.  

      [1] B. Zurita Ares, C. Fischione, K. H. Johansson, “Energy Consumption of Minimum Energy Coding in CDMA Wireless Sensor Networks”, in Wireless Sensor Networks, Springer-Verlag Lecture Notes in Computer Science, Vol. 4373, pp. 212--227, 2007. Available at
      http://www.eecs.berkeley.edu/~fischion/Publications/wsn_lncs07.pdf
      [2] C. H. Liu, H. H. Asada: “A Source Coding and Modulation Method for Power Saving and Interference Reduction in DS-CDMA Sensor Networks Systems”, in Proc. of American Control Conference, 2002.
      [3] Telos: Ultra low power IEEE 802.15.4 compliant wireless sensor module, Moteiv Corporation, 2004, www.moteiv.com/products/docs/telos-revb-datasheet.pdf.
    • Application-level protocols for enhanced dependability in FlexRay:
      Mentors: Paolo Giusto (paolo.giusto@gm.com), Marco Di Natale (marco@sssup.it), Haibo Zeng (zenghb@eecs.berkeley.edu)

      The FlexRay protocol is a new high speed and time deterministic communication protocol for cars, being currently considered for future architectures by essentially all car vendors. The protocol advanced features enable nodes to detect and discard corrupted messages. However, the Flexray protocol delegates the management of the acknowledgement and retransmissions of messages to the application level, this application-level protocol being under the responsibility of designers. As different options exist for allocating the transmission slots of these messages in the time-triggered schedule, tradeoffs exist between the number of tolerated faults, the response times of messages, and the scheduling overhead due to retransmissions and acknowledgments.  We propose the study and evaluation of efficient FlexRay scheduling policies that allow for reliable channels with bounded response times.
    • Slot scheduling for future extensibility in FlexRay:
      Mentors: Paolo Giusto (paolo.giusto@gm.com), Marco Di Natale (marco@sssup.it), Haibo Zeng (zenghb@eecs.berkeley.edu)

    • The development of automotive architectures and applications, which spans over several years, is based upon continuous requirement updates and additions. In these evolving scenarios, components of the architecture, including the serial communication buses and their schedules must be resilient to changes and flexible enough to enable the addition of new functionalities.
      As in FlexRay, scheduling of messages is time triggered and stored in node local tables, schedules and tables must be generated in such a way that free slots must be reserved for future extensions. We propose the study and evaluation of efficient FlexRay scheduling policies that allow for flexible communication cycles with bounded message response times.
    • Scheduling Simulink models in distributed time-triggered systems:
      Mentors: Paolo Giusto (paolo.giusto@gm.com), Marco Di Natale (marco@sssup.it), Haibo Zeng (zenghb@eecs.berkeley.edu)

    • Model-based design flows allow automatic code generation, improving the quality and the efficiency of the design process. Models can be formally verified, simulated, and tested prior to hardware availability.  However, the results of the verification and testing stages are preserved only if the model semantics is preserved by the automatically generated implementation.
      In time-triggered distributed systems, the generation of a semantics-preserving implementation of multirate models requires a careful assignment of the execution and transmission slots to tasks and messages. Scheduling schemes that preserve the model semantics may be difficult to generate, especially when the application also requires the fulfilment of end-to-end deadlines on computations. The development of such a scheduling scheme for commercial models such as Simulink is very important for the correct design of complex distributed systems, including automotive and avionics. We propose the study and evaluation of FlexRay semantic preservation scheduling policies.
    • Simulation of message behaviour and trace analysis in the CAN bus:
      Mentors: Paolo Giusto (paolo.giusto@gm.com), Marco Di Natale (marco@sssup.it), Haibo Zeng (zenghb@eecs.berkeley.edu)

    • The Controller Area Network (CAN) standard is currently the most popular communication standard in cars. CAN allows for bounded message response times and predictable worst case timing behaviour.
      However, commercial middleware and drivers are implemented in ways that prevent the use of standard timing analysis techniques because of the possibility of priority inversion.
      We propose the study of the impact of actual buffer management in CAN to the message latency by using simulation tools and by verifying the results of simulation and the predictions that can be done by using regression techniques on actual message traces.
    • Stochastic Timing Analysis for Hierarchical Shared Resources:
      Mentors: Haibo Zeng (zenghb@eecs.berkeley.edu), Paolo Giusto (paolo.giusto@gm.com), Marco Di Natale (marco@sssup.it)

    • Timing analysis is necessary for real-time embedded systems to provide timing performance information and a good insight for architecture explorations. In many embedded systems, a schedulable object may need to access multiple hierarchical resources to finish its execution/transmission. For example, in CAN message systems, a message first needs to occupy the TxObject (assuming it is not preemptible once it is there) in CAN controllers, then try to compete the CAN bus with other messages. In order to be transmitted, a CAN message needs two levels of resources: first TxObject, then CAN bus.
      As previous work, [1] presents an interesting work of analyzing task response times of periodic real-time systems which is on preemptive schedulers. [2] extends the work in [1] to objects periodicially scheduled with jitter on non-preemptive scheduler, and calculate the Controller Are Networks (CAN) message latency distribution, while assuming the TxObjects in CAN controller are preemptible.
      This project requires the student to extend the work in [1] and [2] to take into consideration multiple resources. To validate the stochastic analysis, a simulation engine also needs to be built up.

      Required Knowledge: Markov chain
      Suggested Number of Students: 2

      [1] J. D´iaz, D. Garc´ia, K. Kim, C.-G. Lee, L. LoBello, J. L´opez, S. Min, and O. Mirabella. Stochastic analysis of periodic real-time systems.  In Proc. of the 23rd IEEE Real-Time Systems Symposium, December 2002.
      [2] Haibo Zeng, Paolo Giusto, Marco Di Natale, Alberto Sangiovanni-Vincentelli, Stochastic Analysis of Controller Area Network Message Latencies. Internal Report.
    • Implementation of different schedulers for managing resource allocation for SystemC functional model processes:
      Mentors: Roberto Passerone (roberto.passerone@unitn.it), Alena Simalatsar (simalats@eecs.berkeley.edu)

    • The existence of incompatible and often competing communication standards entails the idea to create multi-band, multi standard, and reconfigurable “on-the-fly” systems with support of concurrent execution. The realization of flexible and easy adaptable computing platforms that meet cost, physical size, performance and power consumption constrains is very important and it requires a complex design space exploration.
      Previous work [1] was focused on SystemC based methodology for architecture exploration and analysis. A SystemC functional model and processor model were implemented. The functional model consists of part of the UMTS protocol for the User Equipment Domain while the processor model takes the form of a scheduler which manages resource allocation.
      The goal of the proposed project is to extend the library of scheduling policies in order to allow mapping of functional models onto architecture with respect to possible Operating Systems.

      Required Knowledge: C++ or SystemC (required); different scheduling policies (appreciated);
      Suggested Number of Students: 1 + there is one PhD student already working on this project;
      Benefits: possible publication at the end (depends on the results), possibility to get familiar with SystemC language, scheduling policies, and UMTS and some other communication standards.

      [1] Alena Simalatsar and Roberto Passerone, A SystemC-based Methodology for Architecture Exploration and Analysis, internal report.
    • Automatic Generation of the Required Connections between Functional and Architectural Models in SystemC:
      Mentors: Roberto Passerone (roberto.passerone@unitn.it), Alena Simalatsar (simalats@eecs.berkeley.edu)

    • The existence of incompatible and often competing communication standards entails the idea to create multi-band, multi standard, and reconfigurable “on-the-fly” systems with support of concurrent execution. The realization of flexible and easy adaptable computing platforms that meet cost, physical size, performance and power consumption constrains is very important and it requires a complex design space exploration.
      Previous work [1] was focused on SystemC based methodology for architecture exploration and analysis. A SystemC functional model and processor model were implemented. The functional model consists of part of the UMTS protocol for the User Equipment Domain while the processor model takes the form of a scheduler which manages resource allocation. The mapping of the functional model onto a processor is done in an inflexible way which requires some efforts from a programmer in order to make some changes in the mapping.
      The final goal of the proposed project is to facilitate the deployment by automatically generating the required connections between processes of the functional model and scheduler of the processor model in order to allow flexible mapping of functional models onto architecture.

      Required Knowledge: C++ (required); SystemC, different scheduling policies and knowledge of telecommunication standards (appreciated);
      Suggested Number of Students: 1 + there is one PhD student already working on this project;
      Benefits: possible publication at the end (depends on the results), possibility to get familiar with SystemC language, and UMTS and some other communication standards.

      [1] Alena Simalatsar and Roberto Passerone, A SystemC-based Methodology for Architecture Exploration and Analysis, internal report.
    • Extension of the SystemC Functional Models for Design Space Exploration of Software Defined Radios:
      Mentors: Roberto Passerone (roberto.passerone@unitn.it), Alena Simalatsar (simalats@eecs.berkeley.edu)

    • The existence of incompatible and often competing communication standards entails the idea to create multi-band, multi standard, and reconfigurable “on-the-fly” systems with support of concurrent execution. The realization of flexible and easy adaptable computing platforms that meet cost, physical size, performance and power consumption constrains is very important and it requires a complex design space exploration.
      Previous work [1] was focused on SystemC based methodology for architecture exploration and analysis. A SystemC functional model and a processor model were implemented. The processor model takes the form of a scheduler which manages resource allocation, while the functional model consists of part of the UMTS protocol for the User Equipment Domain.
      The goal of the proposed project is to extend the UMTS functional model in order to allow the exploration of multiprocessor systems and realization of functional models of some other communication standards for better exploration of Software Defined Radio platforms.

      Required Knowledge: C++ (required); SystemC and knowledge of telecommunication standards (appreciated);
      Suggested Number of Students: 1 + there is one PhD student already working on this project;
      Benefits: possible publication at the end (depends on the results), possibility to get familiar with SystemC language, and UMTS and some other communication standards.

      [1] Alena Simalatsar and Roberto Passerone, A SystemC-based Methodology for Architecture Exploration and Analysis, internal report.
    • Formal description and SystemC implementation  of the IEEE 802.11 protocol:
      Mentor: Massimiliano D'Angelo (mdangelo@parades.rm.cnr.it)

    • A system-level design approach requires tools which allow the description of the whole system, and a characterization of the sub-systems at different layers of abstraction. With this purpose in mind, PARADES is currently developing DESYRE, a system-level simulator based on SystemC [1].
      At the current stage of the DESYRE project, one of the main focus is the integration of TLM models of wireless protocols. This priority is motivated by the growing interest in the adoption of the wireless technology for monitoring applications.
      The main tasks of this project are:
      1. to provide a formal description of the IEEE802.11 [2] protocol;
      2. to realize its implementation in SystemC.
      The formal description is needed for two reasons:
      1. It reduces the distance between the mostly informal description provided by the standard and the SystemC implementation. Thus, the overall design step is made easier and the result is more likely correct;
      2. It helps to identify orthogonal aspects (e.g. data flow vs control) that can be considered in an indipendent way. This allows to distribute the implementation effort in an efficient way.
      The implementation in SystemC has to be compliant with the structure of the DESYRE simulator.  Information about the simulator environment will be provided by a tutor from PARADES.

      This project is suitable for a group of 3 students. A smaller group is equally welcome; the global effort will be adapted accordingly by reducing the implementation part.
    • Communication-centric modeling and simulation of complex instrumentation and embedded system based on high-end PCI-express interconnect:
      Mentor: Hugo Andrade (hugo.andrade@ni.com)

    • The Communication Synthesis Infrastructure (COSI, http://embedded.eecs.berkeley.edu/cosi/, http://embedded.eecs.berkeley.edu/cosi/Methodology.html, http://embedded.eecs.berkeley.edu/cosi/Publications.html, http://embedded.eecs.berkeley.edu/cosi/Software.html) developed by Alessandro Pinto, Luca Carloni and Alberto Sangiovanni-Vincentelli , allows for the structured, computer-aided development of computing system that need to pay special attention to the communication subsystem.
       
      As mentioned in the article "Instrumentation 2.0: PCIe’s and Multicore’s impact" http://www.electronicproducts.com/ShowPage.asp?FileName=farcnational.jul2007.html, multi-core processors and new communication mechanism such as PCI-express have become very important in the development of new instrumentation systems in particular, and in larger embedded systems in general.  PCI-express (http://www.pcisig.com/specifications/pciexpress/) provides for both back-plane and cabled interconnect, and as such, allows for fairly complex system topology, which can be difficult to design, scale, simulate  and test.
       
      For this project, we would like to use the COSI infrastructure to build a tool that help component providers, system developers, integrators, end-users configure and simulate the effect of various points in the design space to achieve certain figures of merit with regards latency, throughput, reliability, cost, among others. For this purpose, the network is composed of multiple IO boards in PCI-express backplane, a number of such backplanes interconnected through cabled PCI-express and number of computing nodes, in addition to the main host.
       
      To be able to reason about such architectures and accurately model of the PCI-express, busses will be developed and assembled using the COSI framework, such that different trade-offs can be explored.
       
      Applications that can be used as use cases include Software Defined Radio (SDR), and could be modeled using the LabVIEW set of tools.
    • Synthesis of On-Chip Networks Under Hard End-to-End Latency Constraints:
      Mentor: Alessandro Pinto (apinto@eecs.berkeley.edu)

    • Networks on chip have been proposed (http://citeseer.ist.psu.edu/dally01route.html) as a solution to the problem of
      integrating many cores on the same die for future generation SoCs. The general approach to synthesizing on chip networks is to capture the communication requirements among cores in terms of average bandwidth and then derive a network that satisfies such constraints while being optimal with respect to power consumption.

      In this project, we add a latency constraint requirement on each end-to-end communication from a source core to a destination core. The latency requirement can be expressed in seconds or number of clock cycles when the clock frequency is the same for all the clock.

      The students are required to:
      - Define a suitable model to represent latency
      - Define a suitable model to capture on-chip traffic for real time applications
      - Use the models to capture the latency requirements of on-chip communication components and the SoC specification.
      - Formulate an optimization problem for the on-chip network optimization
      - Implement the synthesis algorithm
      - Produce results for some SoCs.

      Prerequisites:
      Max. 2 students. The students shall be enrolled in no more than two courses (including EE249) and should have a strong C++ programming background.
    • Towards an automated mapping from a timed functional specification to a timed architecture:
      Mentors: Hugo Andrade (hugo.andrade@ni.com), Hiren Patel (hiren@EECS.Berkeley.EDU)

    • Over the years, abstraction techniques have most commonly prioritized functionality over predictable timing, resulting in processors that make predictable timing very difficult, if not impossible. In the embedded space, timing and its predictability is far more critical than in general processing and thus, reintroducing timing as a first-class property when thinking about embedded processor design is crucial for advancements in time-critical embedded systems.  To enable this, it is important to not only provide a model of computation that supports explicit timing and concurrency, but that we also have an architecture that provides guarantees to ensure a good mapping between functionality and set of architectures.

      This project leverages the platform-based design methodology by employing LabVIEW ( http://www.ni.com/labview) and its model of computation for functional specification and modeling, PRET architectures (http://chess.eecs.berkeley.edu/pret/) as the set of potential architectures and a set of appropriate mappings between the functions and the architectures.  In the process, we will identify requirements for both the architecture and the model of computation to ensure that such a mapping can be done correctly, consistently and efficiently.
    Timed Structures

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     Last updated 11/27/07