EE 194/290C | 28nm SoC for IoT: The Tapeout Class
The schedule is tentative and still subject to change.
|0||01/16 Tu||Course Information and Overview||Form groups, choose systems to work on|
|01/18 Th||Alumni Panel|
|1||01/23 Tu||Chisel Bootcamp||Learn Chisel|
Learn about system, create goals
List of must-have features
List stretch goals
|01/25 Th||Wireless Basics|
|2||01/30 Tu||Wireless Architecture||Start implementing basic version of block|
|02/01 Th||Wireless Architecture and Modelling|
|3||02/06 Tu||Start testing in Verilator/simulation|
|02/08 Th||Guest Lecture (Fri 2/9, 10am-noon): Dr. Andreia Cathelin from ST|
|4||02/13 Tu||Start testing with neighbouring blocks|
|6||02/27 Tu||Analog schematic design|
Start FPGA testing
|7||03/06 Tu||BLE Guide (David Burnett)||Start testing with entire digital system|
|8||03/13 Tu||28nm Layout Tips (John Wright)||Analog layout|
|9||03/20 Tu||First tape-in|
|10||03/27 Tu||No lecture – Spring break||Take a relaxing and much needed break|
|03/29 Th||No lecture – Spring break|
|11||04/03 Tu||Second tape-in|
|12||04/10 Tu||System co-simulations|
|13||04/17 Tu||Third tape-in|
|17||05/15 Tu||Finish final DRC/LVS fixes|
Submit final reports
Hell is over???
Labs / Homework
- Lab 0 - MATLAB Wireless Homework
- Lab 1 - Synthesis
- Lab 2 - Place and route
- Lab 3 - Programming the RISC-V core
- Lab 4 - Analog characterization and setup
Instructors / GSIs
ResourcesSahar Mesri's thesis - covers in detail the digital system of the Single Chip Mote (SCuM) project. Although our BLE digital system won't be exactly the same, it has many similar modules.
BLEBLE 5 specification, Volume 6 - we will use this document as a reference for meeting the BLE wireless standard specification for the SoC.
Commercial BLE chip - we will use this commercial Bluetooth SoC's datasheet as a reference.
DMADMA overview slides - high-level overview/review of DMA.
Howard Mao's MS thesis - high-bandwidth memcpy/DMA accelerator within L2 cache and main memory.
riscv-dma3 - a RoCC implementation of DMA for rocket-chip. Likely too complex for our chip, but maybe worth a look.
PowerElad Alon's thesis - "Measurement and Regulation of On-Chip Power Supply Noise": a useful resource for designing the on-chip regulators and references.
Digital DesignVLSI: the fab/design interface - overview and history of VLSI.
Combinational logic and blocks - introduction and overview of combinational logic.
Sequential logic from EECS151 Fall 2016 - introduction and overview of sequential logic.
The instructors and TA will post announcements, clarifications, hints, etc. on Piazza. Hence you must check the Piazza page frequently throughout the term. (You should already have access to the forum. If you do not, please let us know.) If you have a question, your best option is to post a message there. The staff (instructors and TAs) will check the forum regularly, and if you use the forum, other students will be able to help you too.
In addition to Piazza, we will also be using the EE 194 Slack workspace to faciliate communication and co-ordination. You should have already received an invitation to join - please contact the instructors/GSI if you do not have access.