Yield Papers
mostly published in the IEEE Transactions in Semiconductor Manufacturing (TSM)
Unified Yield Model TSM 8 96
Statistically Based Parametric Yield Prediction TSM 11 97
Rapid Characterization and Modeling Pattern Dep Var in CMP TSM 2 98
A Study on Failure Prediction in a Plasma Reactor TSM 11 98
Accurate Statistical Process Variation Analysis for 250nm CMOS with TCAD TSM 11 98
An Extraction Method to Determine Interconnect Parasitics TSM 11 98
Circuit Sensitivity to Interconnect Variation TSM 11 98
Defect Propagation Growth on Inline Yield Prediction TSM 11 98
Measurement and Characterization of Interconnect Capacitance TSM 11 98
Expression of Worst Case Using Multivariate Analysis TSM 11 98
Wafer Inspection Technology Challenges for VLSI NIST 99
A Novel Filtering Method to Extract Three Critical Yield Loss Components TSM 11 00
A System Model for Feedback Control and Analysis of Yield TSM 2 01
Fast Extraction of Defect Size Distribution Using a Single Layer Short TSM 11 01
High-Throughput Mapping of Short-Range Spatial Variations using Active Electrical Metrology TSM 2 02
Derivation and Implication of a Novel DRAM Bit Cost Model TSM 5 02
Multivariate Statistical Methods for Modeling and Analysi of Wafer Probe Test Data TSM 11 02
Quantifying the Value of Ownership of Yield Analysis Technologies 11 02
The Impact of Tolerance on Kill Ratio Estimation for Memory TSM 11 02
Process Integration of Single-Wafer Technology in 300mm fab TSM 5 03
A New Accurate Yield Prediction Method for System LSI Embedded Memories TSM 8 03