Introduction to Digital Design and Integrated Circuits

Lectures, Labs, Office Hours

Lectures	Tue, Thu	3:30 pm - 5:00 pm	Online	Sophia Shao
Discussion	Tue	5:00 pm - 6:00 pm	Online	Zhenghan Lin
	Wed	3:00 pm - 4:00 pm	Online	Harrison Liew
ASIC Lab	Tue	8:00 am - 11:00 am	Online	Jingyi Xu
	Wed	5:00 pm - 8:00 pm	Online	Harrison Liew
FPGA Labs	Mon	8:00 am - 11:00 am	Online	Kareem Ahmad
	Thu	5:00 pm - 8:00 pm	Online	Charles Hong
	Fri	1:00 pm - 4:00 pm	Online	Zhenghan Lin
Office Hours	Mon	5:00 pm - 6:00 pm	Online	Charles Hong
	Tue	2:00 pm - 3:00 pm	Online	Sophia Shao
	Tue	6:00 pm - 7:00 pm	Online	Zhenghan Lin
	Wed	2:00 pm - 3:00 pm	Online	Harrison Liew
	Thu	9:00 am - 10:00 am	Online	Jingyi Xu
	Fri	5:00 pm - 6:00 pm	Online	Kareem Ahmad

Homework

Ask questions on our Piazza forum.
Homeworks will be posted as links in the outline below. Please submit completed homework via Gradescope. See Piazza for the entry code.
Homework will be released on Thursdays before midnight, and will be due next Friday 8 days later. Homework will be challenging and graded for correctness.

Exams

Past Midterms and Finals

Course Outline

Week	Date	Lecture Topic	Discussion	ASIC Lab	FPGA Lab	Homework	Homework Solution
1	8/27	Class Organization & Introduction to Course Content slides recording		Lab 1 (Getting Around the Compute Environment) Wed. Recording	Lab 1 (Getting Set Up) Thur. Recording	No homework!
2	9/1	Design Process (Optional reading: H&H: 1.5,1.6, RCN: 1.3) slides recording	Disc. 1: Intro Annotated Slides Tue. Recording Wed. Recording	Lab 2 (Simulation) Wed. Recording	Lab 2 (Introduction to FPGA Development) Fri. Recording	Homework 1 (due 9/11)	Homework 1 Solution
	9/3	Digital Implementation (Optional reading: H&H: A.3-4, RCN: 8.2-8.5) slides recording
3	9/8	Verilog I (Optional reading: H&H: 4.1-4.2) slides recording	Disc. 2: Verilog Basics Anno. Slides (Tues.) Recording (Tues.) Anno. Slides (Wed.) Recording (Wed.)	Lab 3 (Synthesis) Recording (Wed.)	Lab 3 (Tone Generator, Simulation, and Connecting Modules) Fri. Recording	Homework 2 (due 9/18)	Homework 2 Solution
	9/10	Verilog II (Optional reading: H&H: 4.3-4.5) slides recording
4	9/15	Combinational Logic (Optional reading: H&H: 2.1-2.3, 2.7) slides recording	Disc. 3: Verilog Errors, Best Practices, Bubble Pushing, K-Maps Anno. Slides (Tues.) Recording (Tues.) Anno. Slides (Wed.) Recording (Wed.)	Lab 4 (Floorplanning, Placement, Power, and CTS) Recording (Wed.)	Lab 4 (ROMs and IO Circuits) Recording (Thur.)	Homework 3 (due 9/25)	Homework 3 Solution
	9/17	Finite State Machine (Optional reading: H&H: 3.1, 3.4) slides recording
5	9/22	FSM & RISC-V Intro (Optional reading: P&H: 2.1-2.2, 2.5-2.6) slides recording	Disc. 4: FSMs, RISC-V instructions, datapath Anno. Slides (Tues.) Anno. Slides (Wed.) Recording (Wed.)	No new lab!	No new lab!	Homework 4 (due 10/2)	Homework 4 Solution
	9/25	RISC-V Datapath I (Optional reading: P&H: 2.7-2.10) slides recording
6	9/29	RISC-V Datapath II (Optional reading: P&H: 2.7-2.10) slides recording	Disc. 5: RISC-V ISA, Decoding, Datapath, Control Anno. Slides (Wed.) Recording (Wed.)	Lab 5 (Parallelization and Routing) Recording (Wed. #1)	Lab 5 (FSMs and UART) Recording (Thur.)	Homework 5 (due 10/16)	Homework 5 Solution (Updated)
	10/1	RISC-V Pipelining (Optional reading: P&H: 4.5-4.8) slides recording	Midterm 1 Review (Slides) Recording
7	10/6	Midterm 1 Midterm 1 Solutions	Disc. 6: Pipeline Anno. Slides (Tues.) Recording (Tues.) Anno. Slides (Wed.) Recording (Wed.)	No new lab!	No new lab!
	10/8	FPGA (No reading) slides recording
8	10/13	CMOS Transistors and Gates (Optional Reading: RCN: 3.3.1-2, 6.2.1 (up to p.240)) slides recording	Disc. 7: Midterm 1 Anno. Slides (Wed.) Recording (Wed.)	Lab 6 (SRAM Integration, DRC, LVS) Recording (Wed.)	Lab 6 (FIFOs, UART Piano)
	10/15	Inverter Delay (RCN: 5.1-2, 5.4.2) slides recording				Homework 6 (due 10/23)	Homework 6 Solution
9	10/20	Guest Lecture: SoC Engineering	Disc. 8: CMOS Transistors, Gates, Inverters Anno. Slides (Tue.) Anno. Slides (Wed.) Recording (Wed.)	ASIC Project (Checkpoint #1)	FPGA Project Recording (Thur.)
	10/22	Inverter Chain Delay (W&H: 4.4-4.5) slides recording				Homework 7 (due 10/30)	Homework 7 Solution
10	10/27	Logical Effort (W&H: 4.4-4.5) slides recording	Disc. 9: Delay, Sizing, Logical Effort, Power/Energy Anno. Slides (Tues.) Anno. Slides (Wed.) Recording (Wed.)	ASIC Project (Checkpoint #2)	FPGA Project (Checkpoint #1)	Homework 8 (due 11/6)	Homework 8 Solution
	10/29	Wire & Energy(W&H: 6.1-6.3.1, 5.1-5.3) slides recording
11	11/3	Adders (RCN: 11.3) slides recording	Disc. 10: Path Effort, Power/Energy, Adders Anno. Slides (Tue.) Recording (Tue.) Anno. Slides (Wed.) Recording (Wed.)			Homework 9 (due 11/20)	Homework 9 Solution
	11/5	Multipliers (RCN: 11.4) slides recording	Midterm 2 Review Anno. Slides Recording
12	11/10	Midterm 2 Midterm 2 Solutions	Disc. 11: Adders, Multipliers Anno. Slides (Tue.) Anno. Slides (Wed.) Recording (Wed.)	ASIC Project (Checkpoint #3)
	11/5	FlipFlops (RCN: 7.1-7.3) slides recording
13	11/17	SRAM (RCN: 12.2.3) slides recording	Disc. 12: Midterm 2 Anno. Slides (Tue.) Recording (Tue.) Anno. Slides (Wed.) Recording (Wed.)	ASIC Project (Checkpoint #4)		Homework 10 (Due 12/4)	Homework 10 Solution
	11/19	Guest Lecture: Verification
14	11/24	SRAM 2 (RCN: 12.3.1) slides recording	Disc. 13: Latch/FF, Timing, SRAM, Mem. Decoders Anno. Slides (Tue.) Recording (Tue.) Anno. Slides (Wed.) Recording (Wed.)
	11/26	Thanksgiving Holidays!
15	12/1	Other Memory (W&H: 12.2-12.6) slides recording	Disc. 14: SRAM, Cache, DRAM Anno. Slides (Tue.) Anno. Slides (Wed.) Recording (Wed.)	project timeline
	12/3	Finale & What's Next slides recording	Final Exam Review (Slides) Anno. Slides Recording
	12/14	Final Exam solution

Resources

Textbooks

Recommended Digital Design and Computer Architecture, 2nd ed, David Money Harris & Sarah L. Harris (H & H)
Recommended Digital Integrated Circuits: A Design Perspective, Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolić (RCN)
Useful Computer Organization and Design RISC-V Edition, David Patterson and John Hennessy (P&H)
Useful CMOS VLSI Design, Neil Weste, David Harris (W&H)

Verilog

Verilog Primer Slides
wire vs reg, from the CS150 Spring 2009 class.
always@ blocks, from the CS150 Fall 2009 class.
FSMs in Verilog
Ready-Valid Interfaces

Protocols & Standards

Staff

	Sophia Shao	ysshao at berkeley dot edu
	Harrison Liew	harrisonliew at berkeley dot edu
	Charles Hong	charleshong at berkeley dot edu
	Jingyi Xu	jingyixu at berkeley dot edu
	Kareem Ahmad	kareemalgalaly at berkeley dot edu
	Zhenghan Lin	zhenghan_lin at berkeley dot edu

Grading

Class

Problem Sets	20%
Midterm Exam 1	20%
Midterm Exam 2	20%
Final Exam	40%

ASIC Labs

Lab Reports	37.5%
Project	62.5%

FPGA Labs

Lab Checkoffs	25%
Project	75%

Cheating Policy

If you turn in someone else’s work as if it were your own, you are guilty of cheating. This includes problem sets, answers on exams, lab exercise checks, project design, and any required course turn-in material.
Also, if you knowingly aid in cheating, you are guilty.
We have software that compares your submitted work to others.
However, it is okay to discuss with others lab exercises and the project (obviously, okay to work with project partner). Okay to discuss homework with others. But everyone must turn in their own work.
Do not post your work on public repositories like github (private o.k.)
If we catch you cheating, you will get negative points on the assignment: It is better to not do the work than to cheat! If it is a midterm exam, final exam, or final project, you get an F in the class. All cases of cheating reported to the office of student conduct.