///////////////////////////////////////
//
//	LAB5 : FALL '02
//
//Use this as the top level view of your circuit.
//Build the debouncing circuits for the rst_pin signal and the enter_pin signal here.
//Create a module called lock that is instantiated in this module.
//The lock module will contain the FSM and the compare module.
//This module is to be instantiated in FPGA.v which will be synthesized and 
//implemented in the target FPGA.
//
////////////////////////////////////////


module lock_top (clk_pin, rst_pin, enter_pin, code, state_pin, 
		seg1,seg2,seg3,seg4,seg5,seg6,seg7,seg8);


//declare all the ports and all required signals here
input clk_pin;
input rst_pin;
input enter_pin;
input [1:0] code;
output [2:0] state_pin;
output [6:0] seg1, seg2, seg3, seg4, seg5, seg6, seg7, seg8;
reg [6:0] seg1, seg2, seg3, seg4, seg5, seg6, seg7, seg8;

wire out_a;// this is mapped to your openlock output from your FSM
wire out_b;//this is mapped to your error output from your FSM
wire [2:0] states;//this is mapped to the states in your FSM
reg enter; //this is the output of your debouncing circuit
reg reset; //this is the output of your debouncing circuit

wire clk,rst,ent;

assign clk = clk_pin;
assign state_pin = states;
assign rst = ~rst_pin; // the rst_pin is active low
assign ent = ~enter_pin; //the enter_pin is active low



// debounce your enter_pin and your reset_pin here.  //////
//Use as input to your debouncing circuit rst and ent to generate 
//reset and enter respectively.




////////////////////////////////////////
// translate outputs to 7-Segment display
always @(out_a, out_b)
	if (out_a & ~out_b) begin
				seg1 <= 7'b0111111;
				seg2 <= 7'b1110011;
				seg3 <= 7'b1111011;
				seg4 <= 7'b0110111;
				seg5 <= 7'b0000000;
				seg6 <= 7'b0000000;
				seg7 <= 7'b0000000;
				seg8 <= 7'b0000000;
			    end
	else if (~out_a & out_b) begin
				seg1 <= 7'b1111011;
				seg2 <= 7'b0110001;
				seg3 <= 7'b0110001;
				seg4 <= 7'b0111111;
				seg5 <= 7'b0110001;
				seg6 <= 7'b0000000;
				seg7 <= 7'b0000000;
				seg8 <= 7'b0000000;
			    end
	else			begin
				seg1 <= 7'b0000000;
				seg2 <= 7'b0000000;
				seg3 <= 7'b0000000;
				seg4 <= 7'b0000000;
				seg5 <= 7'b0000000;
				seg6 <= 7'b0000000;
				seg7 <= 7'b0000000;
				seg8 <= 7'b0000000;
			    end
///////////////////////////////////////////////


//this is the instantiation of the lock module which contains the FSM 
lock alock (.reset(reset), 
	    .enter(enter), 
	    .code(code), 
	    .clk(clk), 
	    .openlock(out_a), 
	    .error(out_b),
	    .st(states));
endmodule