module dff (C, R, E, D, Q); parameter width = 1; input C, R, E; input [width-1:0] D; output [width-1:0] Q; reg [width-1:0] Q; always @(posedge C) if (R) Q <= { width { 1'b0 } }; else if (E) Q <= D; endmodule module srff (C, S, R, Q); parameter width = 1; input C; input [width-1:0] S, R; output [width-1:0] Q; reg [width-1:0] Q; always @(posedge C) Q <= (S | (Q & ~ R)); endmodule module rsff (C, R, S, Q); parameter width = 1; input C; input [width-1:0] R, S; output [width-1:0] Q; reg [width-1:0] Q; always @(posedge C) Q <= (~R & (S | Q)); endmodule module sr (C, LD, E, I, D, Q); parameter width = 1, out = 1, shift = 1; input C, LD, E; input [width-1:0] I; input [shift-1:0] D; output [out-1:0] Q; reg [width-1:0] Q_; always @(posedge C) if (LD) Q_ <= I; else if (E) Q_ <= { Q_[width-shift-1:0], D }; assign Q = Q_[out-1:0]; endmodule module counter (C, R, E, O, TC, EO); parameter width = 1; input C, R, E; output [width-1:0] O; output TC, EO; reg [width-1:0] O; always @(posedge C) if (R) O <= { width { 1'b0 } }; else if (E) O <= (O + 1'b1); assign TC = (O == { width { 1'b1 } }); assign EO = (TC & E); endmodule module counter_ud (C, R, U, D, O); parameter width = 1; input C, R, U, D; output [width-1:0] O; reg [width-1:0] O; always @(posedge C) if (R) O <= { width { 1'b0 } }; else if (U & ~D) O <= (O + 1'b1); else if (D & ~U) O <= (O - 1'b1); endmodule module SRL32E (C, E, D, Q); input C, E, D; output Q; parameter INIT_00 = 16'h0000; parameter INIT_01 = 16'h0000; wire w0; SRL16E srl0(.D(D), .CE(E), .CLK(C), .Q(w0), .A3(1'b1), .A2(1'b1), .A1(1'b1), .A0(1'b1)); defparam srl0.INIT = INIT_00; SRL16E srl1(.D(w0), .CE(E), .CLK(C), .Q(Q), .A3(1'b1), .A2(1'b1), .A1(1'b1), .A0(1'b1)); defparam srl1.INIT = INIT_01; endmodule module SRL64E (C, E, D, Q); input C, E, D; output Q; parameter INIT_00 = 16'h0000; parameter INIT_01 = 16'h0000; parameter INIT_02 = 16'h0000; parameter INIT_03 = 16'h0000; wire w0, w1, w2; SRL16E srl0(.D(D), .CE(E), .CLK(C), .Q(w0), .A3(1'b1), .A2(1'b1), .A1(1'b1), .A0(1'b1)); defparam srl0.INIT = INIT_00; SRL16E srl1(.D(w0), .CE(E), .CLK(C), .Q(w1), .A3(1'b1), .A2(1'b1), .A1(1'b1), .A0(1'b1)); defparam srl1.INIT = INIT_01; SRL16E srl2(.D(w1), .CE(E), .CLK(C), .Q(w2), .A3(1'b1), .A2(1'b1), .A1(1'b1), .A0(1'b1)); defparam srl2.INIT = INIT_02; SRL16E srl3(.D(w2), .CE(E), .CLK(C), .Q(Q), .A3(1'b1), .A2(1'b1), .A1(1'b1), .A0(1'b1)); defparam srl3.INIT = INIT_03; endmodule module SRL16E (D, CE, CLK, Q, A3, A2, A1, A0) /* synthesis syn_black_box */; input D, CE, CLK, A3, A2, A1, A0; output Q; parameter INIT = 16'h0000; /* synthesis translate_off */ reg [15:0] Q_; initial Q_ <= INIT; always @(posedge CLK) if (CE) Q_ <= { Q_[14:0], D }; assign Q = Q_[{ A3, A2, A1, A0 }]; /* synthesis translate_on */ endmodule