(1) Build a latch, similar to the RS latch, using 2 NAND gates. What is the asynchronous state transition diagram for such a latch.
(2) Could you take the latch above and make it behave like a JK latch? What would you need to do and change? Could you take the latch and further modify it so that it can only change when a third signal (a clock) is high?
(3) Build a 3 bit grey code counter.
(4) Design a 4 bit BCD counter, which has a CEO and TC signals like the xilinx counters do.
(5) Open the schematic for a 8 bit counter in Xilinx (CC8RE). Print it out and provide a written explanation of how it operates. How is this layed out on a Xilinx chip? How is it floorplanned?