CS 150 Homework #11
Due Nov 21st

(1) Take your BCD counter from last week and make any needed modifications to make it self starting.

(2) Take a look at the parallel prefix tree for a fast N bit binary counter. What is the number of AND gates as a function of N? What is the order of growth of the maximum delay.

(3) Some SRAM designs will replace the P type transistor with a very weak pullup. How will reading and writing of the SRAM change? Any other effects this might have?

(4) What would you change in an SRAM to allow you to read two values at a time? What about reading 2 AND writing 1 location simultaneously?

(5) Rereading the Xilinx manual, how many different items can the F-box output to?

This page is maintained by Nick Weaver (nweaver@cs.berkeley.edu)