CS150 Unit 11 page 4

1. Design Constraints.

Usually the design specification puts a restriction on cost, performance, or both. We will leave this unspecified for now and return to this later.

1. Component Library:

Component Delay Notes

n-bit Register clk-to-Q = 0.5ns setup = 0.5 ns

n-bit 2-1 Multiplexor 1 ns

n-bit Adder (2*log(n) + 2) ns

Memory 10 ns read asychronous read

Zero Compare 0.5 * log(n)

These numbers where made up for this example. Are they reasonable?

Component	Delay	Notes
n-bit Register	clk-to-Q = 0.5ns	setup = 0.5 ns
n-bit 2-1 Multiplexor	1 ns
n-bit Adder	(2*log(n) + 2) ns
Memory	10 ns read	asychronous read
Zero Compare	0.5 * log(n)