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CS150 - Spring 2010
Discussion 03
2/8/2010

Chris Fletcher
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Agenda
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The last thing I got to in the first discussion was how to build larger function 
generators using F{7,8} MUXs.  To ensure continuity, I would proceed as follows:

1.) Greeting
2.) Questions (administrative, course in general)?
3.) Verilog (General)
	Types & Overview
		Structural
		Continuous
		Behavioral
	Why does Verilog have C-like constructs?
		--> Used as a simulation-only language
	Where does Verilog get tricky [because of ideosyncrasies in the language, C-like constructs, etc]?
		--> Behavioral Verilog
				always@( ... )
		Behavioral Constructs: 
			Sensitivity lists
				--> Don't use them
			posedge ...
				--> Synchronous blocks
			*
			Simulation ordering (or lack thereof) of events
		Behavioral Statements:
			Blocking
				'Sequential' logic
					--> Sequential is an overloaded term!  Explain sequential vs. combinational logic
				Used to infer COMBINATIONAL logic and priority
				More 'C-like'
			Non-blocking
				'Parallel' logic
				Used to infer STATE ELEMENTS (flip-flops) 
					(a.k.a. sequential logic -- see the confusion?) that react at a clock edge
4.) Case Study (FSM design)
	Parts of an FSM
		State encoding ('parameter' and 'localparam')
		Synchronous transition block
		Combinational decision block
		Outputs
	Show an example (draw on board before the discussion)
	Hazards
		State encoding width
		Two sources of latches [both in state decision block]
			Moving into a state in the case statement and not assigning to one of the regs used in the entire case statement
			Moving into an unknown state/encoding
		Explain difference between default values and 'default' case statement blocks
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