Computer Science 150 Homework Assignment 10
Spring 1997
Due: Thursday, May 8th, 5:00 pm
The numbers in brackets [ ] denote the relative marks assigned for
each question.
This problem concerns the design of a parallel
divider to divide two positive binary numbers (8 bits + 4 bits). The design
should be similar to the one shown below except that in order to speed
up operation of the divider, a shift and subtract operation should take
place simultaneously during a single clock pulse. In order to accomplish
this the wires from the dividend register to the full subtracter in puts
must be shifted one position with respect to the wires from the full subtracter
outputs to the dividend register. In this way the division can be completed
in four clock times.
-
Draw a block diagram for the divider using:
(i) 8 clocked D flip-flops
(ii) 5 full subtracters to perform the necessary
subtraction
(iii) a 4-bit register which holds the divisor
(iv) a block labeled "control circuit"
which puts out the required four pulses when a start signal is applied
(v) any other necessary gates and inverters
Show in detail how the full subtracter inputs
and outputs are connected and how the D flip-flops are connected. The difference
output from the leftmost subtracter is not used. Note that it will be necessary
to gate the subtracter outputs so that when the last borrow bit is B =
1, 0 will be subtracted from the dividend register during the shift and
subtract operation, and when the borrow bit is 0 the divisor will be subtracted
from the leftmost 5 bits of the dividend register during the shift and
subtract operation.[20]
-
If the dividend register initially contains
10010000 and the divisor register contains 1101, show the contents of the
dividend register after each clock pulse.[10]
-
Draw the state diagram for the control circuit
assuming that once the start signal (N) is set to 1 it will remain 1 for
one or more clock times past the completion of the division operation.
Then the start signal will be changed to 0 some time between the completion
of the division and the start of the next division cycle.[20]
(Note: the design of an overflow detector for
this type of divider is fairly difficult and is not required for this problem.)
rnewton@ic.eecs.berkeley.edu