Computer Science 150 Homework Assignment 5
Spring 1997
Due: Thursday, March 13, 5:00 pm
The numbers in brackets [ ] denote the relative marks assigned for
each question.
(1) The following state table
is to be implemented using J-K flip-flops and logic gates (format of next-state
entries is (next-state,output)).
Present
State
|
input
x=0
|
input
x=1
|
|
a
|
a,0
|
e,0
|
|
b
|
c,0
|
b,1
|
|
c
|
a,0
|
f,0
|
|
d
|
c,0
|
b,1
|
|
e
|
f,0
|
e,0
|
|
f
|
a,0
|
f,0
|
(a) Find a good state assignments using the three guidelines mentioned
in class. (Do not reduce the table first). Try to satisfy as many
of the adjacency conditions as possible. [20]
(b) Using this assignment, derive the.J-K flip-flop input equations and
output equations. Express them in a form that contains the minimum number
of literals. [20]
(2) Consider the following state
table for a clocked, synchronous sequential machine, where "-"
represents a "don’t care"
for the value of Z:
| PS
|
NS,
Z
|
|
|
x
= 0
|
x
= 1
|
| A
|
A,
-
|
B,
1
|
| B
|
G,
-
|
D,
0
|
| C
|
B,
1
|
B,
-
|
| D
|
A,
1
|
B,
-
|
| E
|
C,
-
|
A,
-
|
| F
|
F,
-
|
C,
-
|
| G
|
G,
-
|
G,
-
|
Obtain a reduced state table
by eliminating redundant states and by combining equivalent states using
the implication chart method. Show your final implication chart
and include a final version of the reduced state table with the minimum
number of states. [20]
3 Consider the conventional
D latch circuit below left and the alternative circuit shown on the right:
Fig. 1: Conventional D Latch
Fig. 2: Alternative Circuit
(a) Prove that the circuit of
Fig.2 is functionally equivalent to that of Fig. 1. [20]
(b) In what way(s) is the circuit
of Fig. 2 actually better from the standpoint of practical use? List
all possible reasons that it is better. [20]
pchong@cory.eecs.berkeley.edu