Computer Science 150 Homework Assignment 9
Spring 1997
Due: Thursday, May 1st, 5:00 pm
The numbers in brackets [ ] denote the relative marks assigned for
each question.
(1) Consider the following four-input
circuit:
(i) How many conventional stuck-at-0 and stuck-at-1
faults are there in this circuit?[10]
(ii) How many essential faults are there
in the circuit after fault implication and fault equivalences are considered?
List all of them by name.[20]
(iii) List the minimum set of test patterns
needed to test for all essential single stuck-at-1 and stuck-at-0 faults
in the network.[10]
(iv) What patterns would you apply to determine
specifically that the particular stuck-at fault was actually the output
G2.r stuck-at-1 (or the input G3.q stuck-at-1)? (i.e. fault diagnosis)
[10]
(2) (i) Find a hazard-free implementation
of the following function using only 3-input nor gates. Use the minimum
number of gates+gate inputs and assume complements are available. [20]
f(A,B,C,D) = Sum-of-Minterms(0,2,6,7,8,10,13)
(ii) Explain how a hazard in
the next-state logic of a Mealy clocked synchronous machine can affect
the performance of the machine adversely. Consider all cases and recommend
ways of avoiding such adverse outcomes (other than simply eliminating the
hazard by adding additional gates!)[15]
(iii) What are the adverse effects which
might result when one eliminates the hazard by adding additional gates?[15]
rnewton@ic.eecs.berkeley.edu