CS150 Lab 2 Checkoffs
Spring 1997

Name:
Lab Section:

1. Design the IN1, IN2, and MYCLB blocks. Enter it in ViewDraw using only components from the (xc4000) library. You'll probably use the AND2, AND3, OR2, OR3, INV, FDC, and GND components.

   TA:

   (20%)

2. Make a test script for your CLB and run it. Show the TA your script and that the output is correct.

   TA:

   (20%)

3. Design your state register using D-Flip Flops. Call it MYDFF.

   TA:

   (5%)

4. Wire up the FSM using the CLB and state register you designed.

   TA:

   (20%)

5. Write a SpeedWave command file to simulate the following scenarios:
   1. A successful entry of the combination.
   2. A successful entry of the combination with cycles of pauses between when ENTER is asserted.
   3. A sequence with the first combination number entered wrong.
   4. A sequence with the second combination number entered wrong.
   5. A sequence with both combination numbers entered wrong.
   6. RESET is asserted after entering just the first number correctly.
   7. RESET is asserted after entering just the first number incorrectly.

   Create a log file to show your TA.

   TA:

   (25%)

Turned in on time

TA: