CS 150: COMPONENTS AND DESIGN TECHNIQUES FOR DIGITAL SYSTEMS
WEEK 1
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Introduction
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Relationship to other courses in EECS
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What is a Digital Circuit?
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Digital vs. Analog; behavior & waveforms; switches
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Design Example: Word Problem
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Classification of Digital Systems
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Combinational Systems
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Boolean Algebra: History
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Operators: AND, OR, NOT, XOR, EQ
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Truth Tables
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Design Example: Seatbelt Circuit
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Sequential Systems
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Design Example: Car lock
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Introduction to State Graphs and State Tables
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Introduction to Mealy and Moore representations
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Introduction to Design
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The Craft of Design
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Conceptual Blocks & How to Overcome Them
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Good Versus Bad Design
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The Role of Language in Design
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The CS150 Project
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Choosing a Project
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The Flow of the Project: Deadlines!
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Intellectual Property
Reading:
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Katz: 1.1, 1.2, 1.3.1-1.3.4, (1.4), 2.1, 8.1
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Wakerly: 1.1-1.8, 3.1, 7.3.1, 7.3.2, 7.4
Lab:
WEEK 2
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Introduction to Latches and Flip-flops
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Edge triggered D flip-flop
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Master-slave flip flops
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Toggle flip-flops
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Shift Registers & Simple Counters
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Shift register structure
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Serial-parallel conversion
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Ripple, Synchronous, and Ring counters
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LFSR counters
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RAMs, ROMs
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Registers as memory; serial & parallel
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Magnetic and optical memories
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Random-access memory: SRAM, DRAM
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Standard RAM operation: RAS/CAS
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Read-Only Memories
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Bussing, tri-state, multi-porting
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Switch De-bouncing
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FSM Design with ROMs
Reading:
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Katz: 8.2, 6.1.5, 8.4.2-8.4.3, 7.1-7.3, 7.6, 6.6.1
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Wakerly: 7.1, 7.2.5, 7.3.3, 9.3, 9.4, Ch. 11
Lab:
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Lab 1: Introduction to Workview
WEEK 3
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LSI Implementation: PLAs, PLDs, PGAs
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PLA structures & relationship to truth tables
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PLA format
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PLD structures (including memory)
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Field-Programmable Gate-Arrays (FPGAs)
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PROM, EPROM, E2PROM
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Field-programmable ROMs
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E2PROM as a secondary storage option
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Design Example: Car Lock Revisted
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The Xilinx FPGA
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Overview of the Xilinx organization
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Implementing a design on the Xilinx FPGA
Reading:
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Katz: 4.1, 4.2, 10.1-10.4, esp. 10.3.4
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Wakerly: 10.3-10.6
Lab:
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Lab 2: Finite State Machine in Workview
WEEK 4
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Combinational Logic Optimization
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Cube Notation
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Postulates and Theorems of Boolean Algebra
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De Morganís Laws
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Algebraic Simplification
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Standard Forms, Min-terms, Short Form
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Design Example: Simplify algebraically
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Implicants, Prime Implicants, cover, prime cover
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Karnaugh Maps
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What is a Karnaugh Map?
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Relationship to Cube Notation
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Define implicant, prime implicant, cover, prime cover
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Design Example: Simplify using Karnaugh Map
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Multiple-Output Karnaugh Maps
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Input Don't Cares
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Completely vs. incompletely specified logic
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Design Example: Use Karnaugh Map with don't cares
Reading:
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Katz: 2.2-2.4
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Wakerly: 4.3-4.4
Lab:
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Lab 3: Finite State Machine on Xilinx
WEEK 5
18-Feb
slides
(postscript
file)
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Delay Models
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Transition time
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Propagation delay
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Hazards
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Static & Dynamic Hazards
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Glitches
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Hazard-free design
20-Feb
Reading:
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Katz 3.3, 3.4, 3.1, 3.2
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Wakerly: 4.5, 5.4-5.8
Lab:
WEEK 6
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Quiz 1 review
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Multiplexers, Encoders & Decoders
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Multiplexers as function generators
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Priority encoder
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Binary, 7-segment decoder
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Steering Logic
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Switch-level logic
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CMOS transmission gates
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Advanced Topic: the Binary Decision Diagram
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Arithmetic Circuits
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Half adder, full adder
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Ripple carry, carry look-ahead, Carry bypass
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Full adder as full subtractor
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Number Systems
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Sign-magnitude, oneís & twoís complement, BCD, IEEE
formats
Reading:
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Katz: 10.1.4, 2.5
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Wakerly: 6.4-6.8, Ch. 3
Lab:
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Lab 5: Shift Registers and Counters
WEEK 7
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Multiplication, Division, Complex & Multi-step Operations
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Arithmetic Logic Unit (ALU)
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Bandwidth, Latency, Scheduling & Allocation, Pipelining
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Feedback in Digital Circuits
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Bistable and metastable circuits
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Review Latches in Detail
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S-R latch, D latch
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Level-sensitive Latches
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Flip-flops, triggering
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Transformations
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Detailed Design using D and T flip-flops & latches
Reading:
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Katz: 6.1-6.3, 9.1-9.3
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Wakerly: 7.2-7.4, 8.1-8.3
Lab:
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Lab 6: Wirewrapping and EPROMs
WEEK 8
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State Minimization
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Design example: minimize states
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Incompletely specified machines
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State Assignment
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Minimizing latches vs. one-hot
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Binary vs. minimum-distance vs. one-hot vs almost-one-hot codes
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Design example: assign codes to states
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Synchronous State-machine Design
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Overall design flow
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Design example: implement using D flip-flops
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Design example: implement using T
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Invalid states, invalid input sequences
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Timing in Synchronous Sequential Circuits
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Multi-phase Clocks
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Simple examples
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Effect of clock skew
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Partitioning FSMs
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State-of-the-art in CAD for Sequential Synthesis
Reading:
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Katz: 9.4, 9.5, 5.2, 5.1, 5.4
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Wakerly: 9.7, Ch. 2, 5.9
Lab:
WEEK 9
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Asynchronous Circuits
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Moore & Mealy standard forms
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Design Example: word problem
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State Tables and Flow Tables
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State table, transition table, flow table
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Flow table minimization
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Design example: translate to flow table
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Arbiter
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Races and Critical Races
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Hazards & races
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Critical races
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Race-free state assignment
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Design example: race-free state assignment
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Excitation Equations
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Design example: implementation
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Role of essential hazards
Reading:
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Katz: mentioned in 6.4, 6.5
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Wakerly: 7.5, 9.8
Lab:
SPRING BREAK
WEEK 10
1-Apr slides
(postscript file)
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Combining Data & Control
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Control, Datapath, I/O Interfaces
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Introduction to Microprogramming Review for Quiz
2
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Controller Implementation
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Options for implementation of controllers
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Microprogramming
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Partitioning control
Reading:
Lab:
WEEK 11
8-Apr
10-Apr
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Quiz 2 discussion
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Controller Implementation
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Options for implementation of controllers
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Microprogramming
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Partitioning control
Reading:
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Katz: Ch 12 (cont.)
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Wakerly: 8.7
Lab:
WEEK 12
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Combinational Testability and Test-pattern Generation
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Faults in digital circuits
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What is a test? : Controllability & Observability
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Redundancy & testability
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Test coverage & simple PODEM ATPG
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Sequential Testability and Scan Design
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Sequential faults
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Sequential redundancies
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Design-for-test and LSSD
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BILBO
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Estimating Reliability
Reading:
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Katz: <<not covered>>
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Wakerly: 12.2, 12.3
Lab:
WEEK 13
22-Apr
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Review of real chip designs (35mm slides)
24-Apr
Reading:
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Katz: 5.3-5.6, Ch. 11
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Wakerly: 5.9, 5.10
Lab:
WEEK 14
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Sequential design & test review
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Overview and state-of-the-art
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Hamming Codes
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Begin Course Review
Reading:
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Katz: Ch. 11, 12.5
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Wakerly: <<not covered>>
Lab:
WEEK 15
6-May
Reading:
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Katz: <<not covered>>,
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Wakerly: <<not covered>>
Lab: