Table of ContentsOutline Outline Role of Don't-Cares in Logic Synthesis Role of Don't-Cares in Logic Synthesis Role of Don't-Cares in Logic Synthesis Fault Excitation Fault Models Fault Propagation Optimality & Redundancy inCombinational Logic Path-Oriented DEcision Making[Goel, 1981] Cover Extraction Testability and Logic Synthesis Test Generation for Finite-State Machines Finite-State Machines Finite-State Machines Example Finite-State Machine:State Transition Diagram Example Finite-State Machine:Encoded States State Assignment Example Finite-State Machine:Next-State Logic Mealy Machine at Time tn Finite-State Machine as Iterated Array Ideal Iterated Array Sequential Circuits:Controllability & Observability Scan Design Synthesis Procedure for Fully-TestableNon-Scan Finite-State Machine (Devadas, et.al. 1988) Synthesis Procedure for Fully-TestableNon-Scan Finite-State Machines Cascaded Finite-State Machines Coupled Finite-State Machines Example FSMs Constrained State Assignment(single cones) Constrained State Assignment(single cones) Effect of Gate Duplication inStandard-Cell Layout Example Finite-State Machinewith Fault ? Example Finite-State MachineEffect of Fault ? Example Finite-State Machinewith Fault ? Example Finite-State MachineEffect of Fault ? Use of Extended Don't-Care Set toGuarantee Testability(Devadas & Keutzer, '90) Example FSMs Results of Synthesis Procedure Results Using Extended Don't-Care Sets During Synthesis Test Procedure: Scan Test Procedure: Non-Scan What About Testing Time?(Ghosh et. al. 1989) Viterbi Chip What About Testing Time? A Revolution in Test in the Late 1990s? Synthesis-Directed Sequential Test Synthesis-Directed Sequential Test |
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