Deriving the State Diagram and Datapath
Assume Synchronous Mealy Machine:
Transitions associated with arcs rather than states
Reset State (State 0)
and Instruction Fetch
Sequence
On Reset:
zero the PC
Mem Request unasserted
Mem asserts Wait signal
Instruction Fetch:
issue read request
4 cycle handshake on Wait signal
Note: No explicit mention of the
busses being used to implement
register transfers!
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