Table of Contents
Outline
Overall Sequential Design Flow
Common Representations Used in the Design Process
Structured Custom Chip Layout
Standard Cell Layout
Layout Abstractions for Cell-Based Design
Standard Cells vs. Gate Array
Sequential Control-Flow Model
Converting Procedural Descriptions to a Dataflow-Oriented Representation
Complications to Dataflow Analysis*
Complications to Dataflow Analysis
Complications to Dataflow Analysis
Languages versus Models: A Software Analogy
Behavior and Structure: Two Faces of the Same Coin
Behavior and Structure
State and Statements
Data and Control
VHDL: The “nroff/latex” of Design
PPT Slide
3-Bit Parity Function: "Control-Oriented"
3-Bit Parity Function: "Dataflow-Oriented"
3-bit Parity Function:Possible VHDL Implementation
"I synthesize from C" or "I synthesize from VHDL"
Representing Time for Behavioral Description
Why Should Time be Discrete?
Representing Time for Behavioral Descriptions
Encoding Information in Time & Space
Design Representation
PPT Slide
PPT Slide
What's in a Name?
PPT Slide
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