3-bit Parity Function:Possible VHDL Implementation

EE244, Fall 96

6.51

ENTITY parityFunction IS

PORT( A, B, C : IN t_wlogic; parity : OUT t_wlogic )

END parityFunction;

ARCHITECTURE full OF parityFunction IS

BEGIN

PROCESS (A, B, C)

VARIABLE count : integer;

BEGIN
count := 0;

IF A = '1' THEN count := count +1; END IF;
IF B = '1' THEN count := count +1; END IF;
IF C = '1' THEN count := count +1; END IF;
IF (count MOD 2) = 0 THEN
OUT <= '0';

ELSE
OUT <= '1';

END IF;
END PROCESS;

END full;

(Adapted from D. R. Coelho, "The VHDL Handbook," Kluwer, 1989)

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