The specs for exception handling is defined below. Please try not to think too much about this before your basic pipeline is up and running *PERFECTLY*. Remember, it's better to have a working pipeline with no extra credit than a partially working one with both interlock and exceptions implemented. Have fun! =========================================================================== --- Introduction Because of the complexity of exception handling, here is an explanation and simplification of exception handling. Please implement the design as described here. --- Addtional harware required Two Co-Processor-0 registers, EPC and CAUSE. (described below) A 3-bit bus into the processor to determine the cause of external interrupt. Call these Int0, Int1, Int2. (described below in the External interrupt encoding section) State(single bit) to determine whether you are in system mode or user mode. (described below in the system model section) --- System model In the simplified MIPS system model, there are two modes. System and User mode. The processor should start off in User mode and start executing instructions at address 0x00000000. When in user mode, and an exception or interrupt occurs, the processor should flush the pipeline as appropriate and jump to memory location 0x00001000. Note that this is a different address than listed in the manual, and it's at word address 1024 (in decimal). It should also enter system mode and set the appropriate bits in the Cause register. There are five possible types of exceptions: 1) External interrupt 2) Illegal instruction 3) Arithmetic overflow 4) Illegal address 5) Syscall In system mode, only the external exceptions should be blocked. If any other exception occurs while in system mode, then the processor should remain in System mode and unconditionally jump to address 0x00001000. --- Cause register This register is read only. The fields of this register are as follows: bits 2-6: Exception code 0 External Interrupt 4 Address error exception (load or instruction fetch) 5 Address error exception (store) 8 Syscall 10 Reserved instruction exception (illegal instruction) 12 Arithmetic overflow exception bits 8-15: Interrupt pending A 1 set in the decoded bit position of the external interrupt. An external interrupt of (binary) 100 (hex: 0x04) would set bit 12. Note that only one bit will be set at a time. bit 31: Branch Delay Set to 1 when the exception was taken while execution in a branch delay slot. All other bits should be set to 0. --- EPC This read-only register points to the address of the instruction where the exception or interrupt occurred. If the instruction was executing in a branch delay slot, then this should point the address of the branch, and the Branch Delay bit in the Cause register will be set. --- Exception Handlers You must also write code to handle and process exceptions. This code is called the exception handler and should reside at address 0x00001000. When executing the exception handler, the processor is always in system mode The exception handler should behave in the following manner. i) if the exception is not recoverable.. (ie bad inst, arthimetic overflow) then the exception handler enters an infinite loop with the value of the EPC saved at address 0x00000000. ii)if the exception is recoverable (ie external interrupt or syscall) then the exception handler just causes the user program to continue executing. Since external interrupts can't be produced by test code, you should also implement the "syscall" instruction as well. However, since you must jump relative to the EPC upon returning from a syscall exception so that syscall isn't invoked again, you should only handle syscalls that are not in the delay slot of branches or jumps. An exception(arthmetic overflow, bad instruction, bad address) occuring in your exception handler implies that it is broken or written incorrectly. If this is the case, then all bets are off. The exception handler is a piece of code which must be written correctly. Syscall excptions shouldn't occur in system mode since the exception handler has no reason to use this instruction. It already has direct access to all system level routines. --- Additional instructions which must be implemented mtc0 - move to system control coprocessor (this is how you write to registers in the control coprocessor - NOTE: for our simplified version of exception handling, the CAUSE register is read only) mfc0 - move from system control coprocessor (this is how you read EPC and CAUSE register) rfe - return from exception (described below) syscall - generates a syscall exception add - signed add; overflow exception possible sub - signed subtract; ("underflow") overflow exception possible addi - signed add immediate; overflow exception possible --- Return from exception This instruction merely returns the processor to user mode. If this instruction is executed in User mode, it should generate a reserved instruction exception(same as illegal instruction exception). --- External interrupt encoding The three external interrupts bits decode to 7 different interrupts. The value 0 indicates no interrupt. This value should be decoded and placed into the cause register. --- Branches It is *NOT LEGAL* to have two consecutive branch/jump instructions.