Announcements |
1-15-2006 |
Welcome potential students of Fall 06 CS 152!
This website currently reflects Fall 05 CS 152. Feel free to look
around to get a feel for the course. CS 152 is a capstone course for
computer architecture, and features a demanding project in a large
group format (4-5 students per group). Many students report spending
40 hours a week or more on the lab component of the course for a
significant part of the semester.
Note that for Fall 06, completion of EECS 150 at UC Berkeley is a
requirement for undergraduates to take CS 152. Completion of a
logic design course at another university is NOT sufficient -- you
MUST take EECS 150 here BEFORE taking CS 152. This requirement
reflects how closely the CS 152 project relies on CAD tool training
and Verilog project skills developed in EECS 150.
Graduate students are exempt from the EECS 150 requirement. However, graduate
students should consider that CS 152 has a very demanding project
component -- for many graduate students, devoting this much time to
one course is not appropriate. In addition, grading will be done on
the undergraduate curve (mean grade of 2.9-3.3) -- we will not be
grading graduate students on an easier curve. That being said,
graduate students committed to architecture, embedded systems, or CAD
who are confident of their digital design and Verilog skills may find
CS 152 to be a good investment of their time.
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Assignment and Lecture Calendar |
Notes:
- All reading refers to sections in COD unless noted otherwise.
- Lecture notes are available in PDF format (one slide per page).
- PPT exported from Keynote and may show visual artifacts in PowerPoint.
Wk |
Date |
Lecture Topic |
Notes |
Reading |
Assignment |
1 |
M 8/29 |
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T 8/30 |
The MIPS ISA |
PDF PPT |
Ch 2, 3.1-3, 3.8 |
Start on Lab 1; Preview
Lab 2 |
W 8/31 |
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HW 1 available (due at Midterm I review session) |
Th 9/1 |
Single-Cycle Datapaths |
PDF PPT |
5.1-4, 5.8, Appendix B |
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F 9/2 |
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Teams Meet the TA, 12-2 PM, 125 Cory
150 Lab Lecture, 2-3 PM, 125 Cory |
Sa 9/3 |
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Su 9/4 |
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2 |
M 9/5 |
(Labor Day Holiday) |
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T 9/6 |
Single-Cycle Wrap-Up |
PDF PPT |
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Lab 1: Final Report Due, 11:59 PM, via the submit program |
W 9/7 |
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Th 9/8 |
Testing and Teamwork |
PDF PPT |
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Lab 2: Preliminary Design Document due to TAs, 11:59PM |
F 9/9 |
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Lab 2: Design Document Review, 12-2PM or 3-5PM, 125 Cory
150 Lab Lecture, 2-3 PM, 125 Cory |
Sa 9/10 |
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Su 9/11 |
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3 |
M 9/12 |
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Lab 2: Final Design Document due to TAs, 11:59PM |
T 9/13 |
Timing |
PDF PPT |
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W 9/14 |
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Th 9/15 |
Performance |
PDF PPT |
5.5, 5.7 |
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F 9/16 |
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Lab 2: ModelSim Checkoff, 12-2PM or 3-5PM 125 Cory
150 Lab Lecture, 2-3 PM, 125 Cory |
Sa 9/17 |
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Su 9/18 |
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4 |
M 9/19 |
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T 9/20 |
Pipelining I |
PDF PPT |
6.1-4 |
Preview Lab 3 |
W 9/21 |
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Th 9/22 |
Pipelining II |
PDF PPT |
6.5-7 |
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F 9/23 |
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Lab 2: Xilinx Checkoff, 12-2PM or 3-5PM, 125 Cory
150 Lab Lecture, 2-3 PM, 125 Cory |
Sa 9/24 |
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Su 9/25 |
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5 |
M 9/26 |
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Lab 2: Final Report due, 11:59 PM, via the submit program |
T 9/27 |
Pipelining III |
PDF PPT |
6.8-9 |
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W 9/28 |
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Th 9/29 |
Midterm Review Session in Class |
PDF PPT |
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HW 1 due in class
Lab 3: Preliminary Design Document and Team Evaluations due to TAs, 11:59PM |
F 9/30 |
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Lab 3: Preliminary Design Document Review, 12-2PM or 3-5PM, 125 Cory |
Sa 10/1 |
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Su 10/2 |
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6 |
M 10/3 |
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T 10/4 |
Midterm I: 6:00PM to 9:00PM, 310 Soda Hall
(note: no class 11-12:30) |
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W 10/5 |
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Lab 3: Final Design Document due to TAs, 11:59PM |
Th 10/6 |
VLSI |
PDF PPT |
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HW 2 available (due at Midterm II review session) |
F 10/7 |
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Lab 3: Initial Xilinx Checkoff, 12-2PM or 3-5PM, 125 Cory |
Sa 10/8 |
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Su 10/9 |
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7 |
M 10/10 |
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T 10/11 |
Memory Circuits and Interfaces |
PDF PPT |
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W 10/12 |
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Th 10/13 |
Cache I |
PDF PPT |
7.1-2 |
Preview Final Project |
F 10/14 |
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Lab 3: Final Xilinx Checkoff, 12-2PM or 3-5PM, 125 Cory |
Sa 10/15 |
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Su 10/16 |
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8 |
M 10/17 |
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Lab 3: Final Report Due, 11:59 PM via the submit program |
T 10/18 |
Cache II |
PDF PPT |
7.3 |
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W 10/19 |
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Th 10/20 |
Virtual Memory |
PDF PPT |
7.4-5, 7.7 |
Final Project: Preliminary Design Document due 11:59PM.
Team Evaluations due 9PM. |
F 10/21 |
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Final Project: Preliminary Design Document Review, 12-2PM or 3-5PM, 125 Cory |
Sa 10/22 |
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Su 10/23 |
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9 |
M 10/24 |
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Final Project: Final Design Document due to TAs, 11:59PM |
T 10/25 |
Error Correcting Codes |
PDF PPT |
8.2 |
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W 10/26 |
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Th 10/27 |
Advanced Processors I |
PDF PPT |
6.6, 6.9, Yeh and Patt branch prediction
paper.
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F 10/28 |
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Final Project: DRAM Controller Xilinx Checkoff,
12-2PM or 3-5PM, 125 Cory |
Sa 10/29 |
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Su 10/30 |
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10 |
M 10/31 |
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T 11/1 |
Advanced Processors II |
PDF PPT |
6.9-10 |
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W 11/2 |
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Th 11/3 |
Advanced Processors III |
PDF PPT |
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F 11/4 |
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Final Project: Memory System Xilinx Checkoff,
12-2PM or 3-5PM, 125 Cory |
Sa 11/5 |
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Su 11/6 |
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11 |
M 11/7 |
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T 11/8 |
Buses, Disks, and RAID |
PDF PPT |
8.1-2, 8.4 |
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W 11/9 |
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Th 11/10 |
Networks |
PDF PPT |
8.3 |
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F 11/11 |
(Veterans Day Holiday) |
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No Checkoff |
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Sa 11/12 |
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Su 11/13 |
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12 |
M 11/14 |
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T 11/15 |
Routers |
PDF PPT |
MGR Paper |
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W 11/16 |
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Th 11/17 |
Synchronization |
PDF PPT |
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F 11/18 |
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Final Project: Final Checkoff,
12-2PM or 3-5PM, 125 Cory |
Sa 11/19 |
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Su 11/20 |
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13 |
M 11/21 |
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Final Project: Final Report due, 11:59 PM, via the submit program |
T 11/22 |
Multiprocessors |
PDF PPT |
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W 11/23 |
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Th 11/24 |
(Thanksgiving Holiday) |
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F 11/25 |
(Thanksgiving Holiday) |
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Sa 11/26 |
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Su 11/27 |
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14 |
M 11/28 |
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T 11/29 |
BEE2 and RAMP |
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Final Project: Team Evaluations due to TAs, 11:59PM |
W 11/30 |
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Th 12/1 |
Midterm II Review in Class |
PDF PPT |
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HW II due in class |
F 12/2 |
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Sa 12/3 |
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Su 12/4 |
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15 |
M 12/5 |
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T 12/6 |
Midterm II: 6:00PM to 9:00PM, 310 Soda Hall
(note: no class 11-12:30) |
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W 12/7 |
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Th 12/8 |
Last Day: "Lessons Learned" Group Presentations |
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Email Presentation Slides to Instructor by 11:59 PM |
F 12/9 |
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Sa 12/10 |
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Su 12/11 |
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© 2005 UCB
http://www-inst.eecs.berkeley.edu/~cs152/
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