CS 152
Computer Architecture and Engineering
CS 152 Fall 06
TuTh -- 11:00 to 12:30 PM
310 Soda Hall

John Lazzaro | Udam Saini | Jue Sun

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Course Policies and Info

Course Format:

Three hours of lecture and two hours of TA design review per week. A series of computer design project labs are the centerpiece of the course.

Topics: Instruction set design, Register Transfer Level (RTL) machine description. Data-path design. Controller design. Caches and memory systems. Addressing. Microprogramming. Computer arithmetic. Survey of real computers and microprocessors. Computer design projects

Prerequisites: CS 61(c) and EECS 150. For undergraduates, this is a hard requirement. Completion of a logic design course at another university is NOT sufficient -- you MUST take EECS 150 here BEFORE taking CS 152. This requirement reflects how closely the CS 152 project relies on CAD tool training and Verilog project skills developed in EECS 150.

Graduate students are exempt from the "EECS 150 at Berkeley" requirement. However, graduate students should consider that CS 152 has a very demanding project component -- for many graduate students, devoting this much time to one course is not appropriate. In addition, grading will be done on the undergraduate curve (mean grade of 2.9-3.3) -- we will not be grading graduate students on an easier curve. That being said, graduate students committed to architecture, embedded systems, or CAD who are confident of their digital design and Verilog skills may find CS 152 to be a good investment of their time.

Location: Lectures are on Tuesday and Thursday 11:00-12:30, 310 Soda Hall. Design reviews are held in 125 Cory during section (Fridays 12-2 and 3-5). Lab work may be done in 125 Cory or 119 Cory. However, EECS 150 students have priority in 125 Cory: please move into 119 Cory if a 150 student needs a station.


Expanded Description:

This course will give you an in-depth understanding of the inner-workings of modern digital computer systems and tradeoffs present at the hardware-software interface. You will get an understanding of the design process in the context of a complex hardware system, practical experience with computer-aided design tools, and running your designs on real hardware.

Topics include: Instruction set design, computer arithmetic, controller and datapath design, cache and memory systems, input-output systems, networks interrupts and exceptions, pipelining, performance and cost analysis, computer architecture history, and a survey of advanced architectures.

A series of computer design project labs are the centerpiece of the course. The project labs are team projects, with 4-5 students per team. We will implement a major subset of the MIPS architecture three times: once in a single-cycle CPU design, once in a pipelined CPU design, and once in a pipelined CPU with caches and a DRAM controller. Our implementations will be mapped to the gate level and run on FPGA hardware, and will be verified (read: graded by the TAs) using a suite of tricky assembly language programs that test adherence to the MIPS ISA.


Course Materials:


We will be using the third edition of Patterson and Hennessy's Computer Organization and Design book.

The "MIPS RISC Architecture" book may be helpful for the project and will be on reserve in the Engineering Library.

"See MIPS Run" may also be helpful. It will also be on reserve.  

"Computer Architecture: A Quantitative Approach" is an advanced reference, but is not required for the course. It will also be on reserve.  

  • Computer Organization and Design: The Hardware/Software Interface, Third Edition
    by David A. Patterson and John L. Hennessy. (required)
     
  • MIPS RISC Architecture, Second Edition
    by Gerry Kane and Joe Heinrich, Prentice Hall.
    This provides a complete reference on the MIPS instruction set and has very nice treatment of pipelined design.
    (on reserve)
     
  • See MIPS run
    by Dominic Sweetman, Morgan Kaufman Publishers.
    Provides an in-depth, easy to use guide to the MIPS instruction set, including special attention to processor control.
    (on reserve)
     
  • Computer Architecture: A Quantitative Approach, Third Edition
    by John L. Hennessy and David A. Patterson.
    This is a more advanced text, used in CS252. It is available for occasional supplementary reading.
    (on reserve)
     

Course Operation:

    Consult the class schedule for due dates of homeworks and labs.

    There will be 2 long homeworks, based on mid-terms given in previous semesters. The first homework will be released the second day of class, and will be due in class at the first mid-term review session. The second homework will be released after the first mid-term, and will be due in class during the second mid-term review session.

    The homeworks will be graded for effort (did you attempt to solve each problem in a serious way?), not correctness. We will hand out the solutions to the homework at the mid-term review session, to help you study for the mid-term. You may talk about the homeworks with your fellow students, but the homework should represent your own attempt to solve the problem (no copying someone else's answers onto your sheet). The goal of the homeworks is to help you review the material BEFORE the mid-term review session, so that you will get the most out of the review.

    No late homeworks will be accepted.

    The largest factor in your lab grade is how well your group meets its checkoff milestones, particularly the final checkoff, and on the quality and on-time delivery of your final lab reports. In addition, a significant part of your lab grade is based peer reviews from the other members of your group.

    For the laboratory assignments, we will be using the workstations in 125 Cory Hall and 119 Cory Hall. Note that we share 125 Cory with EECS 150, and that class has priority use of 125 Cory. So, you should be prepared to move into 119 Cory if a 150 student needs a machine in 125 Cory. In addition, 2-3 PM Fridays are reserved for 150 Lab Lecture.

    We will be using the class mailing list to communicate updated information; please read your email regularly. You can also post to the mail list, to ask questions of general interest about the labs, homeworks, etc. The class webpage will also be updated regularly (lecture slides, lab bugfixes, etc).


Course Grading:

    The CS Division guideline for an upper division CS class is that the overall class GPA should be between 2.7 and 3.1. Thus, the average grade in this class will be a B or B+. Please set your expectations accordingly.

    There will be two midterm exams covering the material from the readings and class---and no final. They will be given over a 3-hour period in early evening.

    Four labs will total about half of the grade, with relative weighting roughly corresponding to the number of course weeks devoted to the lab. Two mid-terms, two homeworks, peer evaluations, and staff evaluations will make up the remainder of your grade.

    Except for simple clerical errors (totalling points incorrectly, etc) any regrading request to result in a regrading of the entire homework, lab, or mid-term. So, your grade may actually go down instead of up. You have been warned.

    We may impose "regrading deadlines" for a specific lab, mid-term, or homework. No requests for regrades may be submitted after the deadline.


Academic Honesty:

    Like all EECS courses, CS 152 follows the EECS Departmental Policy on Academic Dishonesty. Please read the policy below and become aware of our expectations:

    Copying all or part of another person's work, or using reference material not specifically allowed, are forms of cheating and will not be tolerated. A student involved in an incident of cheating will be notified by the instructor and the following policy will apply:

    1. The instructor may take actions such as:
      1. require repetition of the subject work,
      2. assign an F grade or a 'zero' grade to the subject work,
      3. for serious offenses, assign an F grade for the course.
    2. The recommended action for cheating on examinations or term papers is 1(c).

    3. The instructor must inform the student and the Department Chair in writing of the incident, the action taken, if any, and the student's right to appeal to the Chair of the Department Grievance Committee or to the Director of the Office of Student Conduct.

    4. The instructor must retain copies of any written evidence or observation notes.

    5. The Department Chair must inform the Director of the Office of Student Conduct of the incident, the student's name, and the action taken by the instructor.

    6. The Office of Student Conduct may choose to conduct a formal hearing on the incident and to assess a penalty for misconduct.

    7. The Department will recommend that students involved in a second incident of cheating be dismissed from the University.


 

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