Lab 1
Introductions and Goals
The goal of this laboratory assignment is to familiarize yourself with the Chipyard simulation environment while also allowing you to conduct some simple experiments. By modifying an existing instruction tracer script, you will collect instruction mix statistics and make some architectural recommendations based on the results. You will be conducting cycle-accurate simulations of the “Sodor” instructional cores. These cores were designed to demonstrate basic principles of core design.
This lab consists of two sections: a directed portion and an open-ended portion. Everyone will do the directed portion the same way, and grades will be assigned based on correctness. The open-ended portion will allow you to pursue more creative investigations, and your grade will be based on the effort made to complete the task or the arguments you provide in support of your ideas.
While students are encouraged to discuss solutions to the lab assignments with each other, you must complete the directed portion of the lab yourself and submit your own lab report for these problems. For the open-ended portion of each lab, students must work in groups of two or three. Each group will turn in a single report for the open-ended portion of the lab. You are free to participate in different groups for the different lab assignments throughout the course.
Graded Items
All reports are to be submitted through Gradescope. Please label each section of the results clearly. All directed items need to be turned in for evaluation. Your group only needs to submit one of the problems in the Open-Ended Portion.
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(Directed) Problem 3.4: recorded instruction mixes for each benchmark and answers
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(Directed) Problem 3.5: 1-stage CPI analysis answers
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(Directed) Problem 3.6: 5-stage CPI analysis answers
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(Directed) Problem 3.7: data and the modified section of Chisel source code
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(Directed) Problem 3.8: design problem answers
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(Open-ended) Problem 4.1: recorded ratio, answers, and source code
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(Open-ended) Problem 4.2: instruction definition, test code, worksheet, modified section of Chisel source code
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(Open-ended) Problem 4.3: design proposal and supporting data
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(Directed) Problem 5: feedback on this lab
We strongly recommend finishing the directed portion first before moving onto the open-ended portion of the lab.
Acknowledgments
Many people have contributed to versions of this lab over the years. This lab is based off of the work by Yunsup Lee and was originally developed for CS 152 at UC Berkeley by Christopher Celio, and heavily inspired by the previous set of CS 152 labs (which targeted the Simics emulators) written by Henry Cook. This lab was made possible through the work of Jonathan Bachrach, who lead the development of Chisel, and through the work of Andrew Waterman, Yunsup Lee, David Patterson, and Krste Asanović who developed the RISC-V ISA.
