Introduction and Goals
The goal of this laboratory assignment is to study processor memory hierarchy design by conducting experiments on realistic RISC-V implementations. You will be running simulations of silicon-proven RTL along with a DRAM model.
Graded Items
All reports are to be submitted through Gradescope. Please label each section of the results clearly. The directed portion should be completed individually, and all directed items must be turned in for evaluation. The open-ended portion should be completed in groups of 2-3. Your group only needs to submit one of the problems in the Open-Ended Portion. Only one group member should submit to Gradescope, and the rest of the group members should be added to the submission.
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(Directed) Problem 3.3: answers to questions and relevant supporting data
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(Directed) Problem 3.4: analysis of cache blocking sizes with supporting data
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(Directed) Problem 3.5: analysis of cache parameterization and supporting data
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(Open-ended) Problem 4.1: ccbench plot, parameter values with explanations
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(Open-ended) Problem 4.2: performance analysis, source code, design explanation
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(Open-ended) Problem 4.3: modified code, performance analysis, design explanation
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(Directed) Problem 5: feedback on this lab
Each open-ended option has a detailed section on what materials should be submitted for the report. Make sure to read through that section to ensure you have included all the necessary materials in your submission.
Feedback Portion
In order to improve the labs for the next offering of this course, we would like your feedback. Please append your feedback to your individual report for the directed portion.
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How many hours did the directed portion take you?
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How many hours did you spend on the open-ended portion?
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Was this lab boring?
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What did you learn?
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Is there anything that you would change?
Feel free to write as much or as little as you prefer (a point will be deducted only if left completely empty).
Team Feedback
In addition to feedback on the lab itself, please answer a few questions about your team:
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In a few sentences, describe your contributions to the project.
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Describe the contribution of each of your team members.
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Do you think that every member of the team contributed fairly? If not, why?
Acknowledgments
This lab was heavily inspired by the previous set of CS 152 labs developed by Henry Cook, Yunsup Lee, and Andrew Waterman, which targeted functional simulators such as Simics and Spike. More recent iterations of this lab, developed by Donggyu Kim, David Biancolin, and Albert Magyar, used FireSim to run FPGA-based simulations on Amazon EC2 F1.