Announcements for CS250: VLSI Systems Design

Fall 2009


Thu, Oct 15: Paper for Thursday, October 22th is posted online.

Tue, Oct 13: Papers for Tuesday, October 20th are posted online.

Mon, Oct 12: (Yunsup says:) Office hours for this week (October 16th) will be 1-3pm. Grab me at my office.

Tue, Oct 6: To alleviate the disk quota problem, you can get rid of the following line in the pt-pwr/pt_scripts/pt.time.tcl file. It's on line 156.
# set_power_analysis_options -waveform_format fsdb ...
This file is for the power browser which we don't have license to use. You can go ahead and comment this line out, or copy the file from ~cs250/lab3/v-smipsv2-2stage/build/pt-pwr/pt_scripts/pt.time.tcl to your project directory. Thanks to Scott for pointing this out!
Tue, Oct 6: Lab 3's due date has been extended to Friday, October 9th 12:30PM.
Tue, Oct 6: To make your own temp directory, run /share/b/bin/mkhometmpdir on a Sun Solaris machine. You can use cory.eecs.
Tue, Oct 6: (Yunsup says:) Some people asked me how to get area results, and highlight hierarchy from IC Compiler. I am still in the process of writing tutorials, so in the mean time I assembled a temporary document which addresses these issues. Hope this helps for lab 3 submission. A temporary version of Tutorial 6: Automatic Placement and Routing using Synopsys IC Compiler is available on the web site.

Mon, Oct 5: (Yunsup says:) The SVN quota problem is fixed now. If you are experiencing the same problem again, please contact me right away.
Mon, Oct 5: (Yunsup says:) If Design Compiler is inferring negative edge flip-flops even though you used always @(posedge clk), it is because the standard cell library is broken. The RDFFNX1, RDFFNX2, RSDFFNX1, RSDFFNX2 was coded as a positive edge flip-flops. I fixed the .db file, but I was afraid that this fix will break other people's design which was working correctly with the previous version of the library. If you want to use the new library with this fix, run the following command in your shell before you run Design Compiler:
% export UCB_STDCELLS=synopsys-90nm/typical.negedge

Sun, Oct 4: (Yunsup says:) We are experiencing an SVN quota problem again. We have enough physical disk quota for the drive, however, the SVN is reporting a disk quota problem. I sent out an email to inst. helpdesk, so hopefully they can resolve this problem. I will post a news flash whenever this problem is resolved.

Fri, Oct 2: A link to CS250's Lab Section Survey: press here. (Yunsup says:) This survey is part of my CS301 homework. If you have two minutes to fill out the survey, it will be greatly appreciated!

Wed, Sep 30: Tutorial 8: Pushing SRAM Blocks through CS250's Toolflow (Version 093009a) is available on the web site.

Tue, Sep 29: It seems like you need 250MB to place and route SMIPSv2 core in lab 3. Simulation takes quite a bit of space too. Consider using /home/tmp/ for extra space. Even though /home/tmp/ doesn't show up when you do df -h on the servers, just go ahead and do ls /home/tmp. The server will mount the drive then.
Tue, Sep 29: (Yunsup says:) I'm still working on tutorial 8. Please take a look at ~cs250/examples/v-sram32x512 in the meantime.
Tue, Sep 29: Solutions for Lab 1 and Lab 2 are posted. You can find it at ~cs250/lab1.solution and ~cs250/lab2.solution.

Sun, Sep 27: Acknowledgement section added to all handouts.
Sun, Sep 27: Lab 1: GCD: VLSI's Hello World has been updated to Version 092509a.
Sun, Sep 27: Lab 2: Write and Synthesize a Two-Stage SMIPSv2 Processor has been updated to Version 092509a.
Sun, Sep 27: Lab 3: ASIC Implementation of a Two-Stage SMIPSv2 Processor with On-Chip Synchronous RAM Blocks has been updated to Version 092509a.
Sun, Sep 27: Tutorial 1: Using SVN to Manage Source RTL has been updated to Version 092509a.
Sun, Sep 27: Tutorial 2: Bits and Pieces of CS250's Toolflow has been updated to Version 092509a.
Sun, Sep 27: Tutorial 2: Bits and Pieces of CS250's Toolflow has been updated to Version 092509a.
Sun, Sep 27: Tutorial 3: Build, Run, and Write SMIPS Programs has been updated to Version 092509a.
Sun, Sep 27: Tutorial 4: Simulating Verilog RTL using Synopsys VCS has been updated to Version 092509a.
Sun, Sep 27: Tutorial 5: RTL-to-Gates Synthesis using Synopsys Design Compiler has been updated to Version 092509a.
Sun, Sep 27: SMIPS Specification has been updated.

Thu, Sep 24: Lab 3: ASIC Implementation of a Two-Stage SMIPSv2 Processor with On-Chip Synchronous RAM Blocks (Version 092409a) is available on the web site.

Wed, Sep 23: If you are getting 1 for the IPC, try not to increase the number of instructions when you squash your instruction in the fetch stage. (This is the reason why your IPC is not 1.0)
Wed, Sep 23: If you are using late days, please email the TA after you commit your source code how many late days you used.

Mon, Sep 21: Globally installed ~cs250/install/smips-bmarks have changed. C version of the multiply benchmark ~cs250/lab2/v-smipsv2-2stage/smips-bmarks/multiply/multiply_main.c included in the lab 2 harness has changed as well. A new macro called SET_STATS is defined.You should copy the new version of multiply_main.c to your repository. You don't need to copy the globally installed benchmarks since the makefiles are pointing to the correct path.
Mon, Sep 21: You don't need to implement the mfc0 instruction for lab 2. Normally the mfc0 instruction is used to communicate with the host machine interactively (e.g., system calls) but as you might have noticed lab 2's assembly tests and benchmarks just use mtc0 to halt execution.

Fri, Sep 18: (Yunsup says:) As I mentioned in last section, today's office hours are 1-2pm 611 Soda Hall.

Thu, Sep 10: Tutorial 3: Build, Run, and Write SMIPS Programs has been updated to Version 091009a. The path for the SMIPS benchmarks and test assembly programs were wrong.
Thu, Sep 10: Tutorial 4: Simulating Verilog RTL using Synopsys VCS has been updated to Version 091009b. The path for the SMIPSv1 example was wrong in the Review section.
Thu, Sep 10: Tutorial 5: RTL-to-Gates Synthesis using Synopsys Design Compiler has been updated to Version 091009b. The path for the SMIPSv1 example was wrong in the Review section.
Thu, Sep 10: Tutorial 4: Simulating Verilog RTL using Synopsys VCS has been updated to Version 091009a. The path for the SMIPSv1 example was wrong.
Thu, Sep 10: Tutorial 5: RTL-to-Gates Synthesis using Synopsys Design Compiler has been updated to Version 091009a. The path for the SMIPSv1 example was wrong.

Wed, Sep 9: SMIPS Specification is available on the web site.
Wed, Sep 9: NX server is installed on cory353-{2l,4l,...,24l}.eecs. Notice the pattern is 2*n'l' where 'l' is the lower case of 'L'. (n=1~12). Thanks to inst helpdesk.
Wed, Sep 9: SVN repository is working now. Lab 1's due is September 10th (Thursday) 11:00 AM.
Wed, Sep 9: 12 new servers (8 cores, 8GB RAM each) came. Thanks inst helpdesk! Domains are cory353-{2l,4l,...,24l}.eecs. Currently you can only use NX on cory353-2l. Inst helpdesk is working to get NX installed on rest of the machines. One thing you might noticed is that these machines are sitting in a lab rather than a server room, so there is a possibility that someone might hit the reset button or pull out the power code accidently. Be careful.

Tue, Sep 8: Lab 2: Write and Synthesize a Two-Stage SMIPSv2 Processor (Version 090309a) is available on the web site.
Tue, Sep 8: Tutorial 3: Build, Run, and Write SMIPS Programs (Version 083009a) is available on the web site.
Tue, Sep 8: Tutorial 4: Simulating Verilog RTL using Synopsys VCS (Version 090109a) is available on the web site.
Tue, Sep 8: Tutorial 5: RTL-to-Gates Synthesis using Synopsys Design Compiler (Version 090309a) is available on the web site.

Sun, Sep 6: Notice that when you change your time constraint, you need to change one line in gcdTestHarness_rtl.v. On line 11, you have:
always #5 clk = ~clk;
You need to change 5 to (time constraint specified in constraints.tcl)/2. If your time constraint is 1ns, you should put 0.5
Sun, Sep 6: If you can't meet the 1ns time constraints for W=32, try different options for compile_ultra. For example, get rid of -no_autoungroup, and add -timing_high_effort_script. For further information take a look at dc-user-guide.pdf and dc-reference-manual-opt.pdf. If you can't meet the time constraint, try to increase the clock period until you can meet the time constraints (say 1.2ns) and proceed. In your writeups, specify your clock speed.
Fri, Sep 4: ~cs250/lab1/v-gcd/build/dc-syn/dc_scripts/dc.tcl has changed to report stuff hierarchically.

Thu, Sep 3: Now we have a backup license server. Whenever the primary license server goes down, point to the backup license server. For directions using the backup server please consult the cs250.bashrc script.
Thu, Sep 3: License server update (8:59am). Network connections are back online. Server is working.

Wed, Sep 2: License server update (11:59pm). (Yunsup says:) I got an email from BWRC (where the license server lives) that there is an unexpected network outage. They're working on it.
Wed, Sep 2: The license server seems to be down. (Yunsup says:) Frankly, I don't know how I can fix this problem at 11:39pm. I'll ask tomorrow morning as soon as possible.

Tue, Sep 1: The SVN repository is up and running. Thanks Inst. helpdesk!
Tue, Sep 1: Lab 1: GCD: VLSI's Hello World has been updated to Version 090109a. The SVN repository path has changed. The added line added to point to a global alib-52 was not working. The command line changed to set_app_var alib_library_analysis_path "/home/ff/cs250/stdcells/synopsys-90nm/default/alib". The automated makefile works fine.
Tue, Sep 1: Tutorial 1: Using SVN to Manage Source RTL has been updated to Version 090109a. The SVN repository path has changed.
Tue, Sep 1: Tutorial 2: Bits and Pieces of CS250's Toolflow has been updated to Version 090109b. The path for DesignWare documents has changed. Added Review section.

Sat, Aug 29: There were some premission problems with ~cs250/lab1/v-gcd. It is fixed now. Thanks to the people who let me know.
Sat, Aug 29: The NX server is running on ilinux1.eecs.berkeley.edu! Thanks Inst. helpdesk! Please consult the course info. page for further directions.
Sat, Aug 29: The SVN respository is not up. Inst. helpdesk is working on it. I'll post a news flash when it is ready. For now, work locally.
Please ignore the following:
% svn checkout $SVNREPO/students/yunsup vc
% svn add lab1
% svn add *
% svn commit -m "Initial commit"
% svn update
Please do this:
% cd ~
% mkdir lab1
% cd lab1
% mkdir trunk branches tags
% cd trunk
% pwd
lab1/trunk
% cp -R ~cs250/lab1/v-gcd/* .
Sat, Aug 29: ~cs250/tools/cs250.bashrc only works for bash. You can check what shell you are running by:
% ps
PID TTY TIME CMD
19065 pts/4 00:00:00 bash
19158 pts/4 00:00:00 ps
If you are using a different shell, you're going to find a different process running. In order to change your default shell do the following:
1) Login to update.eecs.berkeley.edu
2) select Change your shell
3) Enter password
4) Enter "/bin/bash"
5) Exit
Sat, Aug 29: There were some permission problems with DVE. It is fixed now. Thanks to the people who let me know.
Sat, Aug 29: Whenever you use compile_ultra for the first time, it is highly likely that it will take quite a while (more than 10 minutes). This is because Design Compiler makes an intermediate representation of the standard cell library to a directory called alib-52. UPDATE: Now this is fixed in Lab 1 Version 082909a.
Sat, Aug 29: Lab 1: GCD: VLSI's Hello World has been updated to Version 082909a. A line for Design Compiler has been added to make the tool point to a global alib-52. The change is on page 8. The command line added is set_app_var alib_library_analysis_path "~cs250/stdcells/synopsys-90nm/default/alib". Other changes are minor.
~cs250/lab1/v-gcd/build/dc-syn/Makefile and ~cs250/lab1/v-gcd/build/dc-syn/scripts/dc_setup.tcl have changed as well to incorporate the same change. You can simply copy these two files to your working directory.
Sat, Aug 29: Tutorial 1: Using SVN to Manage Source RTL has been updated to Version 082909a. Fixed some misspelled words.
Sat, Aug 29: Tutorial 2: Bits and Pieces of CS250's Toolflow (Version 082909c) is available on the web site.
Sat, Aug 29: Documentation for Synopsys tools, and standard cells are available on ~cs250/docs/manuals. Please consult Tutorial 2 for further information.
Fri, Aug 28: Lab 1: GCD: VLSI's Hello World (Version 082809a) is available on the web site.
Fri, Aug 28: Tutorial 1: Using SVN to Manage Source RTL (Version 082809a) is available on the web site.