Handouts for CS250: VLSI Systems Design
Fall 2011
Labs
Lab 1: GCD: VLSI's Hello World
September 7th: Version without chisel(Lab 1a)
Lab 2: Write and Synthesize a Two-Stage RISC-V Processor
Lab 3: ASIC Implementation of a RISC-V Core with On-Chip Caches
Tutorials
Chisel Tutorial
Use this tutorial,
combined with slides from lecture, as your Chisel reference. Check back here
periodically for updates.
Tutorial 1: Using Git to Manage Source RTL (Version 082311)
Tutorial 2 (Version 091210a): Bits and Pieces of CS250's toolflow
- Version 083010a: initial posting
- Version 090110a: changed manuals directory
- Version 091210a: add link for HDL Compiler for Verilog User Guide
Tutorial 3 (Version 091110b): Build, Run, and Write RISC-V Programs
- Version 091110a: initial posting
- Version 091110b: minor typo fix
Tutorial 4 (Version 091210a): Simulating Verilog RTL using Synopsys VCS
- Version 091110a: initial posting
- Version 091210a: major change. need to change lab
harness. now pc+4 relative.
Tutorial 5 (Version 091210b): RTL-to-Gates Synthesis using Synopsys Design Compiler
- Version 091210a: initial posting
- Version 091210b: major change. need to change lab
harness. now pc+4 relative.
Tutorial 6: Automatic Placement and Routing using Synopsys IC Compiler
Tutorial 7: Power Analysis using Synopsys PrimeTime PX
Tutorial 8: Exploring a Technology Kit (Synopsys 90nm Educational)
Tutorial 9: UC Berkeley's SRAM Model Compiler
Tutorial 10: Generating SRAMs in Chisel
Berkeley Architecture Research Infrastructure
The RISC-V Instruction Set Manual