Handouts for CS250: VLSI Systems Design
Fall 2013
Labs
Lab 1: GCD: VLSI's Hello World - updated 09/09/13
Lab 2: RISC-V, Spike, and the Rocket Core - updated 09/17/13
Lab 3: Your First Accelerator: Matrix Sum - updated 10/09/13
Lab 4: Putting It All Together - updated 10/24/13
Tutorials
Using Git to Manage Source RTL
Discussion Sections
Access to the discussion slides is now restricted to Berkeley IP addresses, as some discussions contain content from Synopsys tools and libraries.
Please do not redistribute these materials or repost them publicly.
Discussion 1 Slides: Course logistics and Unix software basics.
See also the commands used during section.
Here are my .bashrc and .bash_profile scripts;
here are some more involved ones, courtesy of Brian Zimmer.
Discussion 2 Slides: Makefiles, git, vim, and Python.
Discussion 3 Slides: Standard cells and timing.
Discussion 4 Slides: SRAMs in Chisel.
Discussion 5 Slides: Ready-valid interfaces, register retiming, and design space exploration with Chisel.
Discussion 6 Slides: Bash, TCL, and the Synopsys tools.
Discussion 7 Slides: Low-power design in Synopsys, and taping out chips.
Documentation
These two documents (along with the slides from lectures 2 and 3) comprise the bulk
of the reference material on Chisel currently available.
Chisel Tutorial
Chisel Manual
To learn more about Chisel, visit the Chisel Homepage.
Documentation on the RISC-V ISA: RISC-V Spec - compiled on 9/03/2013
For more information on the new RISC instruction set, visit riscv.org.
Here are a few documents on the Rocket scalar core, a hardware implementation of RISC-V designed in Chisel.
(Note: These references have not been updated recently and may be out of date.)
These are not public-facing documents and so are only available from Berkeley IP addresses.
Overview, Pipeline,
Cache, Virtual Memory
Synopsys Application Notes
Access to all Synopsys materials is restricted to Berkeley IP addresses. Please do not redistribute these materials or repost them publicly.
These documents describe some key features and best practices for datapath design using Synopsys tools.
Coding Guidelines for Datapath Synthesis
DesignWare Datapath and Building Block IP Quick Reference
Tutorial: Power-Performance Optimization of Digital Circuits
Access to all Synopsys materials is restricted to Berkeley IP addresses. Please do not redistribute these materials or repost them publicly.
These slides give a good overview of the area/energy tradeoffs in VLSI design.
The first set focuses on digital circuit optimization in general, and the second set deals specifically with the Synopsys ASIC tool flow.
Part 1: Digital Circuit Optimization
Part 2: Low-Power Synthesis/Labs
Synopsys 90nm Digital Design Workshop slides
Access to all Synopsys materials is restricted to Berkeley IP addresses. Please do not redistribute these materials or repost them publicly.
These slides provide a thorough explanation of all facets of an ASIC physical design flow, using Synopsys tools and targeting their 90nm educational library.
They are in PowerPoint format - make sure to read the presenter notes associated with each slide.
Some of the topics covered (e.g. design for testing, improving yield, etc) aren't relevant for CS250, but most of them are.
Lecture 1: Intro: What are the new challenges to design 90nm SOCs?
Lecture 2: Design environment and tool chain
Lecture 3: Design synthesis
Lecture 4: Leakage aware design/prevention (esp. SRAMs)
Lecture 5: Design Planning/Floorplanning (FP) for Low Power
Lecture 6: Library analysis and management (standard cell, IO, memory)
Lecture 7: Low Power Flow, positioning the different techniques to minimize dynamic and leakage power, consequence on the flow
Lecture 8: Physical Synthesis: Placement and optimization
Lecture 9: Multiple Clock Tree Synthesis
Lecture 10: Physical Synthesis: Test
Lecture 11: Physical Synthesis: MultiMode and MultiCorner
Lecture 12: Physical Synthesis: Routing to GDS2
Lecture 13: IR drop analysis, requirement to do dynamic power analysis in 90nm
Lecture 14: Introduction to multimode multi-corner simulation. Introduction to OCV (On-chip variation) and SSTA (Statistical Static Timing Analysis)
Lecture 15: Sign-Off
Lecture 16: Design finishing & layout verification
Lecture 17: Tape-out