All blame to: Arya Reais-Parsi, aryap at berkeley dot edu

Introduction

The purpose of this lab is to familiarise you with the efabless OpenLane VLSI design flow and the Skywater 130nm PDK. OpenLane is an open-source VLSI flow built around open-source tools. That is, it’s a collection of scripts that run these tools, in the right order, transforming their inputs and outputs as appropriate, and organising the results (like Berkeley’s own HAMMER.)

OpenLane and the 130nm PDK are the result of a recent, concerted effort by various industry players to democratise ASIC design. To understand the project, watch the introductory presentations made by various key contributors:

  1. TODO(you): [FOSSi Dial-Up] Tim Ansell - Skywater PDK: Fully open source manufacturable PDK for a 130nm process
  2. TODO(you): [FOSSi Dial-Up] Mohamed Shalan - OpenLane, A Digital ASIC Flow for SkyWater 130nm Open PDK

And for interest:

Collaboration and communication

This is a collaborative learning process! We will get the most it of this by sharing our discoveries and ideas as we go along. To that end, please join the class Slack channel and be attentive to people’s messages.

Please avoid Piazza for technical help.

TCL

For reasons that will become obvious, most digital design flows use or heavily rely on TCL scripts in some way. TCL (“Tool Command Language”) is designed specifically to address the need to run multiple disparate tools and glue them together. It’s less complicated than Python and more sane than any shell script.

It’s straightforward to read, but a non-trivial grasp of the language will be invaluable in your career as an electronic design engineer (or even as a software engineer).

A lot of OpenLane is written in TCL.

TODO(you): Work through the first ~15 sections of the TCL Tutorial.

Set up instructions

We are working on setting up instructional machines for your use. A key benefit of using an open-source tool flow, though, is that you can run it at home. For this lab we will try to do just that.

OpenLane is distributed as source that compiles and is packaged into a Docker app. Docker is sort of like a container, and uses a lot of the same kernel functions, but is actually proprietary third-party software for isolating applications. In this case, it enables OpenLane to package specific versions of their dependencies together.

TODO(you):

  1. Install Docker for your platform.
  2. Install Magic VLSI from source or using the package manager for your platform.
  3. Follow the OpenLane set up instructions and make sure the test design spm works. Use the default PDK_VARIANT.

We will call your OpenLane installation directory OPENLANE_ROOT. For example, if I git clone git@github.com:efabless/openlane.git /home/arya/some_dir, I would export OPENLANE_ROOT=/home/arya/some_dir.

NOTE Getting Docker to run might be tricky for some platforms. For Debian 10, I had to modify my boot config to get Docker to run.

NOTE Once Skywater 130 and OpenLane are installed, the Docker run command assumes that you have $PDK_ROOT set to the directory in which you put the various PDK repositories (and to which open_pdks installed the artifacts).

Make sure you set PDK_ROOT every time you open a new shell. Or at least, make sure it’s an environment variable whenever you run the docker command. A convenient way to avoid having to remember where this is to create a sourceme.sh script in your PDK_ROOT that sets the variable to the directory its located in:

$ cat sourceme.sh
export PDK_ROOT=$(readlink -f "$(dirname "${BASH_SOURCE[0]}")")

But readlink isn’t super-portable, so your system might need an alternative.

A toy example: gcd.v

Now for the juicy part. We’re going to create a new design in OpenLane, add some Verilog we baked earlier, and run the whole flow. Then we’ll look at the outputs.

  1. Create a new design in OpenLane 
    # Make sure PDK_ROOT is set!
cd ${OPENLANE_ROOT}
docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) openlane:rc2

    In the container, run:

    ./flow.tcl -design gcd -init_design_config

    The has now created ${OPENLANE_ROOT}/designs/gcd and a basic config.tcl configuration script.

  2. Go there and add the pre-baked sources: 
    cd ${OPENLANE_ROOT}/designs/gcd
wget https://inst.eecs.berkeley.edu/~cs250/fa20/files/gcd.tar.xz
tar xJf gcd.tar.xz
rm gcd.tar.xz
  3. Modify config.tcl to set the clock frequency constraint, make sure the clock port name matches the clock port in gcd.v (hint: the default should be fine).
  4. Run flow.tcl in the docker container: 
    docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) openlane:rc2
# container starts
./flow.tcl -design gcd
  5. Wait
  6. Once the run is complete, you should see a new directory in ${OPENLANE_ROOT}/designs/gcd/runs/. It’ll be named after the UTC time pertaining to the run. Call that subdirectory LATEST_RUN and descend into it. You should see logs, reports, results, tmp. If you see errors.log or errors.txt, that is bad.
  7. Look at the timing reports in ${LATEST_RUN}/reports/synthesis.
  8. What is the critical path?

Currently, by default, no power report is generated. You can enable it by uncommenting these lines in ${OPENLANE_ROOT}/scripts/sta.tcl:

 29 report_power
 30 report_power > $::env(opensta_report_file_tag)_power.rpt

Once modified, re-run the flow and look at the power report (also in ${LATEST_RUN}/reports/synthesis).

View layout

The final output of the flow is a GDSII file containing all of the ASIC geometry. We can view it with either Magic VLSI or kLayout.

kLayout

  1. Install kLayout for your platform, by package manager or from source.
  2. Set up the Skywater 130 technology in kLayout:
  3. Go to Tools > Manage Technologies
  4. Right click on the Technologies pane and select Import Technology
  5. Navigate to ${PDK_ROOT}/sky130A/libs.tech/klayout and select sky130A.lyt
  6. This will create the EFS8A technology. Close the Technology Manager window and select EFS8A with the technology toolbar button (it’s a big T in a circle).
  7. Open the GDSII file ${LATEST_RUN}/results/magic/gcd.gds.
  8. Play with viewing different layers. (NOTE: These should be named. Why are they not named?)

Design-space exploration

OpenLane comes with a convenient mechanism for running flows with a range of configuration options.

  1. Define a “regression” configuration file in ${OPENLANE_ROOT}/designs/gcd/regression.config:
CLOCK_PERIOD=(1 2 5 10)
GLB_RT_ADJUSTMENT=(0 0.15)
FP_CORE_UTIL=(10 25 50)
PL_TARGET_DENSITY=(0.05 0.1 0.2)
SYNTH_STRATEGY=(1 3 14)

extra="
"

There is some documentation for these parameters here. See also this explanation of FP_CORE_UTIL vs PL_TARGET_DENSITY.

NOTE: The scripts generate the Cartesian product of options, which is in this case 324 different runs. That’s a lot! Remove some of the configuration parameters you don’t really care about. Or try to isolate one or two dimensions to sweep at a time only.

Set up the regression config and run the regresion tool to find the tightest clock timing for the design, for example:

cd ${OPENLANE_ROOT}
docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) openlane:rc2
# in the container:
python3 run_designs.py --designs gcd --regression designs/gcd/regression.config --threads 4