CS61C Machine Structures. Fall 2004, UC Berkeley
CS61C Fall 2004: Project 3 - Verilog MIPS Processor

TA in Charge: Andrew Schultz

Due Wednesday, November 24, 2004, 11:59pm

Project Specification | Frequently Asked Questions | Contact


Project Specification

Autograder tests: http://inst.eecs.berkeley.edu/~cs61c/hw/proj3/autograder-tests/
Project specification: (pdf) | (html)

P&H Appendix C.2

Note: There has been a revision to "Makefile" you can get the new version at http://inst.eecs.berkeley.edu/~cs61c/hw/proj3/Makefile This should fix issues with iverilog not spitting out error messages (see wiki or newsgroup for more info).

Note: There has been a revision to "make_test.pl" you can get the new version at http://inst.eecs.berkeley.edu/~cs61c/hw/proj3/tests/make_test.pl The "proj3.tar.gz" and "proj3.zip" files have been updated as well.


Revision history

2004.11.20 - Fixed Rs/Rt ordering on diagrams and make higher quality images
2004.11.18 (2:10pm) - Fixed typo "make_perl.pl" -> "make_test.pl"
2004.11.18 (12:00pm) - Fix minor typo ("not the semantics" -> "note the semantics")
2004.11.17 - Original copy of specification


Frequently Asked Questions

2004-11-17 As an experiment, I have setup a Wiki that we can use to do questions/answers. I will cull FAQs from the newsgroup and put them in the Wiki too. Give the Wiki a try if you are interested, I'm curious to see if you all find it useful. You can find it at http://ascender.eecs.umich.edu/proj3


Contact

Contact me on AIM: cs61ctb
Contact me by email cs61c-tb@imail.eecs
Use anonymous remailer to submit questions or feedback here

CS61C-tb, http://inst.eecs.berkeley.edu/~cs61c/hw/proj3/ (Last Updated: 2004-11-17 ALS )