CS61C
Fall 2004
Lab 09 - Intro to Verilog

Purpose

To familiarize you with the basic syntax of Verilog.

Reading

Sections 1 - 6 of the Verilog Tutorial. Please note, if you printed this off before Monday, 10/25 you may have an outdated version. Check the revision date near the top.

Background

By convention, Verilog files end in ".v". The command to compile such files is

iverilog -tvvp -Wall -o <output filename> <input files>
which is available only on nova.cs.berkeley.edu. Option -tvvp indicates that the output is a complete program that simulates the design but must be run using the command vvp. -Wall displays all warnings. If you're interested, you can get more details on the options by running man iverilog.
To run the output file, use the command
vvp <output filename>

Description

For this lab we shall write and test a circuit that performs the increment operation on a two-bit counter. The truth table for the operation is given below:

         in1     in0     out1     out0
          0       0       0        1
          0       1       1        0
          1       0       1        1
          1       1       0        0

You are given 3 files, which include 2 testbenches testincrement.v and testincrement2.v, as well as increment.v which contains the incomplete module increment. These are located in ~cs61c/labs/lab09/.

Part 1: The boolean equation relating output out0 to inputs in1 and in0 is simply (out0 = not in0). What is the most concise boolean equation for the output out1 in terms of the inputs?

Part 2: The testbench testincrement.v is complete, but has 1 bug. Identity that bug (hint: it is on the line that instantiates our increment module).

Part 3: The module file increment.v is incomplete. Complete it by filling in the equivalent of the boolean operations found in Checkoff 1 above. You must implement the boolean operations in structural Verilog, that is, you can only use the modules and, or, not, xor, nand, nor, xnor and buf. Show your TA your working testbench and module by compiling and running them using the following commands. Save the output to a file to show your TA when you get checked off...

iverilog -tvvp -Wall -o testincrement testincrement.v increment.v

vvp testincrement

Part 4: testincrement2.v is a slightly modified version of testincrement.v. We instantiated a slightly different version of increment, but the basic functionality remains exactly the same: it still takes in two-bits, and returns those two-bits incremented by 1. Modify increment.v so that it works with testincrement2.v, and save the resulting file as increment2.v. Show your TA that you get the same results by compiling and running the modified files.