# CS61C Fall 2014 Homework 3 Part 2

TA: Riyaz Faizullabhoy

Due Sunday, October 5th, 2014 @ 23:59:59

## Goals

This assignment will cover floating point numbers, and caches.

## Exercises

### Problem 1: Floating Points - 10pts

If you're starting this homework early and we haven't covered this yet don't worry. We'll be going over floating point representation in Friday's lecture. For the following questions, we will be referring to the IEEE 32-bit floating point representation except with a 6 bit exponent (bias of 2^6/2 - 1 = 31) and a denorm implicit exponent of -30.

2. Convert the floating point number 0x98765000, which follows the 6 bit exponent representation as described above, to decimal. Please specify infinities as +inf" or -inf, and not a number as NaN.

3. What's the smallest non-infinite positive integer (an integer has nothing to the right of the decimal) it CANNOT represent? Leave your answer in decimal (ex: 12).

4. What's the smallest positive value it can represent that is not a denorm? Leave your answer as a power of 2 (ex: 2^x).

5. What's the smallest positive value it can represent? Leave your answer as a power of 2 (ex: 2^x).

### Problem 2: Caches - 4pts

Assume we have 16 bit byte-addresses. A very tiny direct-mapped cache holds a total of 32 bytes and each cache block is a word wide.

1. How many bits are used for the tag?

2. Which other bytes would share a block with the byte at address 0x75? Please write the bytes in hex (ex: 0xAA) in your answer, and separate multiple answers by single spaces, if you wish to include more then one byte in your answer (ex: 0xAB 0xFF)

3. The block containing the byte at 0x75 is in the cache. What memory accesses are guaranteed to get a cache miss? Specify what the value of the index bits equate to, in decimal.

4. The hit time is a clock cycle, and the miss penalty is 100. If the miss rate is 50%, what is the AMAT? Please specify your answer in decimal (ex: 12.5)

### Problem 3: Cache Memory Accesses (from P&H Computer Org. & Design) - 6pts

The following C program is run (with no optimizations) on a processor with a direct-mapped cache that has eight-word (32-byte) blocks and holds 256 words of data:

```int i,j,c,stride,array;
...
for(i=0; i<10000; i++)
for (j=0; j<512; j+=stride)
c += i%(array[j]);
```

If we consider only the cache activity generated by references to the array and we assume that integers are words, what possible miss rates (there may be multiple) can we expect

1. if `stride` = 256?
2. if `stride` = 255?