CS61C Fall 2014 Homework 4

TA: Riyaz Faizullabhoy, Rohan Chitnis

Due Sunday, November 9, 2014 @ 11:59pm



This assignment will check your understanding of synchronous digital systems, state elements, and combinational logic.


Submit your solution by creating a directory named hw4 that contains hw4.txt. (File names are case-sensitive and the submission program will not accept your submission if your file names differ at all from those specified) From within that directory, type submit hw4. Partners are not allowed on this assignment.

Copy the contents of ~cs61c/hw/04 to a suitable location in your home directory to obtain files you will want for this homework.

$  cp -r ~cs61c/hw/04 ~/hw4 


Problem 1: Waveform Diagrams - 4 pts

waveform circuit.jpg

Consider the circuit of Flip-Flops (FF) shown here. Assume that input X alternates between 1 and 0, 10ns after every rising edge. Initially, X is 0 (so 10ns after the first rising edge it should be 1) while A, B, C, and D are unknown. Assume one clock cycle is 30 ns. Given the clock signal, draw the wave for input X, and the signals at points A, B, C, and D in the circuit for the first 6 clock cycles. Assume that the clk-to-q delay is 5 ns, the setup time is negligible (~0 ns), and the hold time is 5ns. Assume that Flip-Flops take their new value on the rising edge of the clock cycle. Assume time = 0 on the first rising edge. Note the NOT gate that precedes B (you may ignore propagation delay for this problem).

Answer the following questions. You would want to fill out the waveform diagram below to help though you don't have to submit it. Consider six clock cycles (so six rising edges) as shown in the diagram. Assume the diagram is cut off 5ns after the last rising edge. You only need to consider from t = 0 ns to t = 155 ns for this problem.

  1. How many times does the value at B change (changing from undetermined to 1 or 0 counts as one)?
  2. How many times does the value at D change (changing from undetermined to 1 or 0 counts as one)?
  3. At which time(s) does the value at A becomes stable at 0?
  4. At which time(s) does the value at C becomes stable at 1?

Problem 2: Clock Frequency - 3 pts

Consider this circuit. It accumulates two arguments at a time, arriving at each clock period. You are given the following: the adder propagation delay is 1 ns, the register setup time is 2 ns, the register hold time is 2 ns, the register clk-to-q delay is 3 ns, and the clock frequency is 100 MHz.

clock frequency circuit.jpg
  1. Would this accumulator work properly? Explain why or why not.
  2. Now assume that the arguments arrive 2 ns after each clock period. Give the critical path delay and the maximum clock frequency at which the circuit will work.
  3. Describe a way to rearrange the accumulator so that the maximum clock frequency will be greater. You may only use the components already present in the circuit.

Problem 3: Simple FSM and Truth Tables - 3 pts

Design an FSM that would take an infinite stream of bits and output 1 twice if it sees two consecutive 1's. In other words, given some input Xi, if Xi-2 = Xi-1 = 1 or Xi-1 = Xi = 1, then it will output 1. Then convert it into a truth table mapping each state and input to a next state and an output. Name the states meaningfully so that it is easily understandable (for example, Seen1 and Seen11). You should have at most four states only. You only need to submit the truth table; you do not need to submit your drawing of the FSM.

Problem 4: Truth Tables, Boolean Algebra, FSMs, Logic Circuits - 5 pts

Consider the following finite state machine.
  1. Come up with the MOST simplified boolean expressions for determining bits for the next state and the output bit given the current state and the input bit. You should have 3 expressions, one for each digit of the next state as well as one for output. (You might want to first construct a truth table.).

    Please label the left bits as Curr_1 and Next_1 for start state and next state left bits, respectively, and do the same for right bits Curr_0 and Next_0.

  2. fsmCompute takes one bit at a time as input. Fill in the blanks below so that it behaves as according to the FSM above. Hint: your expressions from part a should come in handy, along with some bitwise operators. Also, note how the state is a static variable, so it is maintained across function calls.
    	Called once per "clock cycle."
    	Assume input x is 0 or 1.
    	Updates state and outputs FSM output (0 or 1).
    int fsmCompute(int x) {
    	int retval;
    	static unsigned int state = 0x1;
    	retval = ______________________;
    	state = _______________________;
    	return retval;