Due Sunday, November 9, 2014 @ 11:59pm
Updates
Goals
This assignment will check your understanding of synchronous digital systems, state elements, and combinational logic.
Submission
Submit your solution by creating a directory named hw4
that contains hw4.txt.
(File names are casesensitive and the submission program will not
accept your submission if your file names differ at all from those
specified) From within that directory, type submit hw4
. Partners are not allowed on this assignment.
Copy the contents of ~cs61c/hw/04
to a suitable location in your home directory to obtain files you will want for this homework.
$ cp r ~cs61c/hw/04 ~/hw4
Exercises
Problem 1: Waveform Diagrams  4 pts
Consider the circuit of FlipFlops (FF) shown here. Assume that input X alternates between 1 and 0, 10ns after every rising edge. Initially, X is 0 (so 10ns after the first rising edge it should be 1) while A, B, C, and D are unknown. Assume one clock cycle is 30 ns. Given the clock signal, draw the wave for input X, and the signals at points A, B, C, and D in the circuit for the first 6 clock cycles. Assume that the clktoq delay is 5 ns, the setup time is negligible (~0 ns), and the hold time is 5ns. Assume that FlipFlops take their new value on the rising edge of the clock cycle. Assume time = 0 on the first rising edge. Note the NOT gate that precedes B (you may ignore propagation delay for this problem).
Answer the following questions. You would want to fill out the waveform diagram below to help though you don't have to submit it. Consider six clock cycles (so six rising edges) as shown in the diagram. Assume the diagram is cut off 5ns after the last rising edge. You only need to consider from t = 0 ns to t = 155 ns for this problem.

Problem 2: Clock Frequency  3 pts
Consider this circuit. It accumulates two arguments at a time, arriving at each clock period. You are given the following: the adder propagation delay is 1 ns, the register setup time is 2 ns, the register hold time is 2 ns, the register clktoq delay is 3 ns, and the clock frequency is 100 MHz.

Problem 3: Simple FSM and Truth Tables  3 pts
Design an FSM that would take an infinite stream of bits and output 1 twice if it sees two consecutive 1's. In other words, given some input X_{i}, if X_{i2} = X_{i1} = 1 or X_{i1} = X_{i} = 1, then it will output 1. Then convert it into a truth table mapping each state and input to a next state and an output. Name the states meaningfully so that it is easily understandable (for example, Seen1 and Seen11). You should have at most four states only. You only need to submit the truth table; you do not need to submit your drawing of the FSM.
Problem 4: Truth Tables, Boolean Algebra, FSMs, Logic Circuits  5 pts
Consider the following finite state machine.

