CS61C Fall 2014 Lab 12 - Project 4 Prelude

Advanced Logisim Features

Here are two more logisim features you will find useful. After reading about tunnels and extenders, begin the lab exercises below.


A tunnel allows you draw an "invisible wire" to bind two points together. Tunnels are grouped by case-sensitive labels give to a wire. They are used to connect wires like so:

Which has an effect such as the following:

Some care should be taken as to which wires are connected with tunnels to which other wires, such as in this case:

Which in turn has the following effect:

We strongly recommend you use tunnels with Logisim, because they make your circuits much cleaner looking, and therefore easier to debug.


When changing the width of a wire, you should use a bit extender for clarity. For example, consider the following implementation of extending an 8-bit wire into a 16-bit wire:

Whereas the following is much simpler, easier to read, and less error-prone:

Additionally consider the case of throwing out bits. In this example, an 8-bit wire is being converted into a 16-bit wire by throwing out the other bits:

Despite the implications of its name, a bit extender can also do this same operation:

Lab Exercises

Copy the starter lab files as usual, from the directory: ~cs61c/labs/12

Exercise 1: Logisim ALU

In this exercise, you will first implement a 32 bit ALU in logisim. As a reminder, recall that ALU stands for Arithmetic Logic Unit. An ALU is a fundamental building block of a CPU (central processing unit) and it performs integer arithmetic and logical (bitwise) operations. The function that the ALU performs (e.g. add, xor) is determined by the control of our datapath, which is determined by the instruction the processor is executing. The ALU is highlighted in a simplified datapath diagram below:

This lab assignment is similar to the CPU design project (it is essentially a slightly simpler version of Project 4's ALU). Hopefully by getting a headstart here in lab, Project 4 will go a bit more smoothly!

The 8 functions that you will implement are: shift left logical, shift right logical, shift right arithmetic, rotate left, rotate right, and, or, and xor. The ALU will perform a desired function on 2 32-bit inputs and output the result. The selected function will be determined by the value of the control signal, as listed below.

Here's what occurs for each operation:

Control Operation
000 Shift Left Logical
001 Shift Right Logical
010 Shift Right Arithmetic
011 Rotate Left
100 Rotate Right
101 And
110 Inclusive Or
111 Exclusive Or


Exercise 2: Register File

Recall that a register file is an array of registers in a CPU. We use the register file to read or write from chosen registers. The regfile is highlighted in a simplified datapath diagram below:

This exercise will help you understand how a register file works, and give you more practice with Logisim. For your project 4 processor, you will be given a register file circuit to use.

Your regfile will contain 4 registers. Just like in our MIPS processor, we require register 0 to always equal 0, so you should not be able to write any values into register 0.

The inputs of your circuit are:

The outputs of your regfile should be:


  • Be sure to understand the purpose of all of the pins found on a register.
  • When constructing your regfile, you may find a demux to be helpful.


  • First set the contents of some registers manually, and show your TA that reading from RS and RT works.
  • Now set RD=11 and RD_WRITE_ENABLE=1 and demonstrate writing a value into register 3. Ensure the value on the REG_3_VALUE only changes on the rising edge of the clock, and that no other registers change values.
  • Next, set RD=11 and RD_WRITE_ENABLE=0 and tick the clock. Test that REG_3_VALUE does not change because the WRITE_ENABLE input is not high.
  • Set RD=00 and RD_WRITE_ENABLE=1 and attempt to write a value into register 0. Its value should not change because register 0 should always equal 0.