CS61C Homework 7

CPU Datapath and Control Design

Due:2008.04.10 @ 11:59pm
TA:Keaton Mowery <cs61c-tk@imail.eecs.berkeley.edu>



This assignment will ensure that you understand the basics of CPU datapath and control design.


Read P&H 5.1-5.4


P&H Exercise 5.1 (reproduced below)

Do we need combinational logic, sequential logic, or a combination of the two to implement each of the following:

  1. Multiplexor
  2. Comparator
  3. Incrementer/Decrementer
  4. Barrel Shifter
  5. Multiplier with Shifters and Adders
  6. Register
  7. Memory
  8. ALU (the ones in single-cycle and multiple-cycle datapaths)
  9. Carry Look-Ahead Adder
  10. Latch
  11. General Finite State Machine

P&H Exercise 5.2 (reproduced below)

Describe the effect that a single stuck-at-0 fault (i.e., regardless of what it should be, the signal is always 0) would have for the signals shown below, in the single-cycle datapath (Figure 5.17). Which instructions, if any, will not work correctly? Explain why.

Consider each of the following faults separately:

  1. RegWrite = 0
  2. ALUop0 = 0
  3. ALUop1 = 0
  4. Branch = 0
  5. MemRead = 0
  6. MemWrite = 0

P&H Exercise 5.3 (reproduced below)

This exercise is similar to Exercise 5.2, but this time consider stuck-at-1 faults (the signal is always 1).

P&H Exercise 5.8 (reproduced below)

We wish to add the instruction jr (jump register) to the single-cycle datapath (Figure 5.17) described in this chapter. Add any necessary datapaths and control signals to the single-cycle datapath and show the necessary additions to the following table (Figure 5.18).

Instruction RegDst ALUSrc MemToReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOp0
R-Format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 0 0 1 0 1

(See Figure 5.18 for more explanation)

P&H Exercise 5.9 (reproduced below)

This question is similar to Exercise 5.8 except that we wish to add the instruction sll (shift left logical), which is described in Section 2.5.

P&H Exercise 5.13 (reproduced below)

Consider the single-cycle datapath (Figure 5.17). A friend is proposing to modify this single-cycle datapath by eliminating the control signal MemToReg. The multiplexor that has MemtoReg as an input will instead use either the ALUSrc or the MemRead control signal. Will your friend's modification work? Can one of the two signals (MemRead and ALUSrc) substitute for the other? Explain.

Submission Details

Create a directory named 'hw7' containing a README and any additional files needed for your submission. The README should say where to look for each question's solution. While in that directory, run 'submit hw7'. For your included images, make sure to say "yes" when the submit script prompts you about it. Please only submit images in the following formats: GIF, JPG, and PDF.