In this assignment, you will implement a 16 bit ALU in logisim. This lab assignment is part of the CPU design project; hopefully by getting a headstart here in lab, Project 4 will go a bit smoother!
Functions
The nine SISD functions that you will implement are: add, subtract, OR, AND, shift left logical, shift right logical, shift right arithmetic, set less than, and EQUAL. The ALU will perform a desired function on two 16-bit inputs (A and B, where a0 is the lowest order bit for A, etc...) and output the result (RESULT). The function will be determined by the value of a control signal (S), as listed below.
In addition we will include four SIMD functions: ADD a pair of Packed 8 bit numbers (addp8), SUBtract a pair of Packed 8 bit numbers (subp8), MULtiply a pair of Packed 8 bit numbers (mulp8), and DIVide a pair of Packed 8 bit numbers (divp8).
In addition to the 16 bits of output provided in RESULT, three additional outputs will be provided: unsigned overflow, signed overflow and equal. Unsigned overflow will have a high value iff the command was an add and unsigned overflow occured. Signed overflow will have a high value iff the command was an add or a subtract, and signed overflow occured. (You need not worry about unsigned overflow for subtractions.) Equal will have a high value when the two inputs are IDENTICAL, and will have a low value at all other times. Notice how the equals signal is generated REGARDLESS of the value of the control signal S.
For the SIMD instructions overflow should be reported if either of the additions or subtractions overflow.
For the shift instructions detailed below (sll, srl, sra), the shift amount is ONLY the 4 least significant bits of B. You can ignore the other bits of B.
Here's what occurs for each operation:
S | opp | Result |
---|---|---|
0000 | add | A + B (signal if either type of overflow occurs) |
0001 | sub | A - B (signal if signed overflow occurs) |
0010 | sll | A << B[3:0] (but logically, don't sign extend!) |
0011 | srl | A >> B[3:0] (but logically, don't sign extend!) |
0100 | sra | A >> B[3:0] (but arithmetically, do sign extend!) |
0101 | slt | if (A < B) //Treat X and Y as SIGNED! then result = 1 else result = 0 |
0110 | or | A | B |
0111 | and | A & B |
1000 | mulp8 | {A[15:8] * B[15:8] , A[7:0] * B[7:0] } //The SIMD product of 2 pairs of 8 bit numbers. |
1001 | divp8 | {A[15:8] / B[15:8] , A[7:0] / B[7:0] } //The SIMD quotient of 2 pairs of 8 bit numbers. |
1010 | addp8 | {A[15:8] + B[15:8] , A[7:0] + B[7:0] } //The SIMD sum of 2 pairs of 8 bit numbers. |
1011 | subp8 | {A[15:8] - B[15:8] , A[7:0] - B[7:0] } //The SIMD difference of 2 pairs of 8 bit numbers. |
XXX | eq | A == B (Have this value be on the equals output regardless of selection) |
On Built-in logic blocks
In project 4, you will have no restrictions on what logic blocks you may use. That said, we think you will get the most out of this assignment if, and therefore encourage you to, only use tools from the "Base", "Gates", and "Wiring" libraries in Logisim. You can always strip out your homebrew adder and replace it with a logisim-adder based version if you're feeling nervous about your implementation.
You will not need any items from the Memory library. Your ALU should be stateless. We reserve the right to dock points on Project 4 for unjustifiable design decisions.
Details & Hints
- LABEL EVERYTHING!
- You can download logisim for yourself as well as view more documentation at the logisim website: http://ozark.hendrix.edu/~burch/logisim/
- You can and should use multi-bit wires! Before or after placing a gate you can select the bit width of that gate. This means the number of bits which run through the input and output pins of that gate. For example, a 2 bit wide AND gate with two wires coming in and 1 wire going out actually is taking a 4 bit input and a 2 bit output. The gate performs the one bit AND function on each respective pair of inputs: it ANDs the two lowest order bits and outputs the result on the lowest order bit of the output, etc... The wires will automatically be the width of the input/output pin they are connected to, and Logisim will be kind enough to immediately report any inconsistencies in pins connecting to the same wire.
- Whether built on your own or borrowed from Logisim's libraries, please use subcircuits! They make it easier for you, they make it easier for us. Give your subcircuits, and their input/output wires, appropriate labels as well.
- The key to your sanity on this project is modularity. Don't be afraid to build subcircuits that are multiple levels deep.
- A quick reminder: Signed overflow only has meaning when thinking of numbers represented in two's complement form. By definition, signed overflow occurs when:
- the sum of two positive numbers is negative
(Example w/ 4-bit numbers: 0100 + 0100 = 1000) - the sum of two negative numbers is non-negative
(Example w/ 4-bit numbers: 1000 + 1000 = 0000) - subtracting a positive number from a negative one yields a positive result; or
- subtracting a negative number from a non-negative one yields a negative result.
- the sum of two positive numbers is negative