CS61C Lab 13

Virtual Memory



The purpose of this lab is to acquaint you with the structure and workings of the virtual memory system. You will work with two different simulators to develop this understanding.



You will be using camera again this week, but instead of working with the cache simulator, you'll want to click the "Virtual Memory and Paging" option when you start the application. To load camera, run:

$ java -classpath ~cs61c/bin/camera Camera

After selecting the VM option, what you will see is a visualization of a virtual memory system. In the top left you can see the contents of physical memory. Just below that is a listing of all the pages of the virtual memory of this process. To the right of these items you'll see the contents of the TLB and the Page table. At this point these should all be empty as we haven't done anything yet. Read about the statistics of your memory system in the "PROGRESS UPDATE" box at the bottom of the window. This area will keep you updated on your status through the simulation as it progresses.


VMSIM is a virtual memory simulator located here: http://cne.gmu.edu/workbenches/vmsim/vm.html


Exercise 1: A Sample Run (CAMERA)

Click the button labeled "Auto Generate Add. Ref. Str." at the right-hand side of the window. This will generate a set of ten address references. You can think of these as a series of MIPS "load word" instructions reading from the memory address specified. Click the button labeled "Next" to begin the simulation.

For the rest of this exercise you are at the mercy of the "PROGRESS UPDATE" box. After each click of the "Next" button examine the contents of the box and the current state of the memory system. Try to really get an understanding of what is going on in the TLB, the Page Table, and Physical Memory at each step.

Once you have reached the end of the simulation note the number of TLB Hits and Misses and Page Hits and Faults. Write these numbers down, along with the sequence of memory accesses used to show to your TA during checkoff. Did you have any Page Hits? Why or why not?

Exercise 2: MISS! (CAMERA)

Now that you've seen what a random workload looks like in the VM system let's try creating a custom workload with a specific property. Your goal for this exercise is to create a workload of ten memory accesses that will cause ten TLB misses and ten Page Faults. You should be able to come up with such a workload on paper, but then you should run it in CAMERA to verify your work. You can specify a custom workload in CAMERA by clicking the button labeled "Self Generate Add. Ref. Str." and entering in the addresses you want to reference one at a time. When you are satisfied that you've got a valid sequence write it down and be ready to show it to your TA during checkoff.

Exercise 3: Memory Systems Engineering (CAMERA)

Given your sequence of memory accesses from Exercises 2, can you find a change to a single parameter (e.g. TLB size, page table size, memory size, etc...) that would result in the same number (ten) of TLB misses but result in fewer than ten page faults? Work through this on paper and be ready to show your results to your TA during checkoff.

Exercise 4: Putting it all in Context (VMSIM)

Go to the VMSIM website and inspect the VMSIM applet. What is different about the setup of this simulation as compared to CAMERA? In particular, what are P1, P2, P3, and P4? If you watch closely you'll see that this simulation reports a much higher percentage of TLB misses than the random run on CAMERA did. Why might this be?