CS61C Su07 Homework 7

CPU Datapath and Control Design

Background

TA: Valerie Ishida <cs61c-tc@imail.eecs.berkeley.edu>
Due: Thursday, August 2, 23:59:59
Goals: Practice with processor datapath and control
Reading: P&H: 5.1-5.4

Problems

All the questions for this week are from the P&H book.
Complete exercises 5.1, 5.2, 5.3, 5.8, 5.9, 5.13.

The exercises are reproduced below.

5.1 <Sec 5.2> Do we need combinational logic, sequential logic, or a combination of the two to implement each of the following:

  1. multiplexor
  2. comparator
  3. incrementer/decrementer
  4. barrel shifter
  5. multiplier with shifters and adders
  6. register
  7. memory
  8. ALU (the ones in single-cycle and multiple-cycle datapaths)
  9. carry look-ahead adder
  10. latch
  11. general finite state machine

 

5.2 <Sec 5.4> Describe the effect that a single stuck-at-0 fault (ie., regardless of what it should be, the signal is always 0) would have for the signals shown below, in the single-cycle datapath in Figure 5.17 on page 307. Which instructions, if any, will not work correctly? Explain why.

Consider each of the following faults separately:

  1. RegWrite = 0
  2. ALUop0 = 0
  3. ALUop1 = 0
  4. Branch = 0
  5. MemRead = 0
  6. MemWrite = 0

 

5.3 <Sec 5.4> This exercise is similar to Exercise 5.2, but this time consider stuck-at-1 faults (the signal is always 1).

 

5.8 <Sec 5.4> We wish to add the instruction

jr
(jump register) to the single-cycle datapath described in this chapter. Add any necessary datapath or control signals to the single-cycle datapath of Figure 5.17 on page 307 and show the necessary additions to Figure 5.18 on page 308. You can photocopy these figures to make it faster to show the additions.

 

5.9 <Sec 5.4> This question is similar to Exercise 5.8 except that we wish to add the instruction

sll
(shift left logical), which is described in Section 2.5.

 

5.13 <Sec 5.4> Consider the single-cycle datapath in Figure 5.17. A friend is proposing to modify this single-cycle datapath by eliminating the control signal MemtoReg. The multiplexor that has MemtoReg as an input will instead use either the ALUSrc or the MemRead control signal. Will your friend's modification work? Can one of the two signals (MemRead and ALUSrc) substitute for the other? Explain.

 

Submission

You should submit your homework electronically using the command:

submit hw7

For questions that require diagram drawings, you may use any graphics drawing programs of your choice, as long as it can produce one of following output format: PDF, PNG, PS, GIF, JPG.