There are two parts to this lab. In the first part, you will be learning how to use the remaining essential parts of logisim, in particular, learning how to maintain state and how to split wires to take a subset of bits on a wire. The second part will allow you to familiarize yourself with the general approach of splitting a finite state machine into two parts: the controller, which maintains the current state, and the next-state and output circuit combinational functions.
P&H section B.10 (copy can be found here). Refer to the Logisim Website or last week's lab for a refresher on Logisim.
The following exercises will teach you how to store state into logisim as well as introduce you to how wires work in logism.
Let's implement the circuit you worked on in Lab 8. The difference between this circuit and the circuits you've built for lab so far is that you need some registers. The following will show you how to add registers to your circuit.
You may notice that when you connect the adder to a register, you will get a "Incompatible widths" error. This means that your wire is trying to connect two pins together with different bit widths. If you click on one the adder with the "Selection" tool, you will notice that in the box below circuit browser will have a field called "Data Bit Width". This field controls the number of bits the the adder will add. Change this field to 8 and the "Incompatible widths" error should now go away.
In general, the box below the circuit browser will list the properties of a given circuit element. Other circuit elements will have other properties.
Now lets see if you built your circuit correctly.
Note: You can use Simulate->Go In To State->*Circuit Name*, but that allows you go into the first circuit of that type. If you placed two Fib8 circuits down, it only takes you to the first Fib8 circuit to put down.
Show your Fib8 circuit to your TA. |
Now that you are familiar with combinational designs in Logisim, we will experiment designs with stateful elements.
Appendix B in P&H presents a description of a circuit used to control a traffic light. Your job in this part of the lab is to implement and test the traffic light controller in Logisim.
The details of the traffic light controller finite state machine are explained in P&H. You should follow that specification with one modification. Add an input signal called RST. Asserting this signal should "reset" the controller to the NSgreen state (on the next positive clock edge) regardless of its current state and the value of the other inputs. Otherwise your circuit should be identical to the one described in the book.
Create a sub-circuit that implements the next-state combinational logic for the trafic light.
Show your sub-circuit to your TA |
Create a circuit that implements the traffic light controller. This module must include an instance(s) of your next-state combinational logic and a flip-flop to hold the current state. Test it with a couple of input cases.
Show the controller to your TA |
Devise a scheme to test your circuit. You want some way to test all possible inputs and easily verify that they produce the correct output. Try to come up with something more clever than manually flipping the inputs and verifying the outputs and something more reliable than connecting clocks with different frequencies to the inputs.
Show how you test your design to TA |