Create a directory named 'hw8' containing the file
hw8.txt and any additional
files needed for your submission. While in that directory, run 'submit hw8'. For your included images, make sure to say "yes" when the submit
script prompts you about it. Please only submit images in the following
formats: GIF, JPG, and PDF.
Problem 1
Consider the simple
single-cycle datapath , and the signals:
- RegDst
- MemRead
- MemtoReg
- MemWrite
- ALUSrc
- RegWrite
For each of the above control signals, list one TAL MIPS instruction that will
not function correctly under the following scenarios:
- stuck-at-0 fault (i.e., the signal is always 0)
- stuck-at-1 fault (i.e., the signal is always 1)
Problem 2
Consider the same
single-cycle datapath .
A friend is proposing to modify this single-cycle datapath by eliminating
the control signal MemToReg. The multiplexor that has MemtoReg as an input
will instead use either the ALUSrc or the MemRead control signal. Will your
friend's modification work? Can one of the two signals (MemRead and ALUSrc)
substitute for the other? Explain.
Problem 3
Consider, again, the same
single-cycle datapath .
The following table describes the control signals for several instructions: (See Figure 5.18 for more explanation)
Instruction |
RegDst |
ALUSrc |
MemToReg |
RegWrite |
MemRead |
MemWrite |
Branch |
R-Format |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
lw |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
sw |
X |
1 |
X |
0 |
0 |
1 |
0 |
beq |
X |
0 |
X |
0 |
0 |
0 |
1 |
Suppose we wish to add the instructions
-
jr
(jump register) and
-
sll
(shift left logical)
to the datapath. Add any necessary datapaths and control signals to the current single-cycle datapath, and fill in the missing entries for these instructions.
Include any control signals that you might have added.
Problem 4
With the same
single-cycle datapath , assume the following latencies:
Adder |
ALU |
Data Memory |
Inst. Memory |
Register File (read/write) |
50ps |
150ps |
400ps |
250ps |
100ps |
Assume further that MUX, sign-extender and shifters have negligible latencies.
- Compute the latencies for each of the 5 stages.
- For the current single-cycle implementation, what is the maximal clock frequency?
- If using a pipelined implementation, what is the maximal clock frequency?