CS 61C, Summer 2010
Due Monday, August 9, 2010 @ 11:59:59pm
TA in charge: Tom Magrino (email@example.com)
Since we want you guys to focus on the third project, we're trying to keep the homework pretty simple for this final assignment. We want you guys to complete the following problems from P&H (THESE ARE BASED ON THE FOURTH EDITION, WE HAVE NOT CONFIRMED WHETHER THE PROBLEMS ARE THE SAME IN THE THIRD EDITION. Expect an update later with the problems copied onto this page for those of you who can not get access to the book) and put your answers in a plaintext file named README. Below are the problems we want you to complete:
Below are the questions copied verbatim from the book:
5.4 For a direct-mapped cache design with 32-bit address, the following bits of the address are used to access the cache.
Starting from power on, the following byte-addressed cache references are recorded.
5.8 (This exercise is supposed to be done assuming the addresses you're given are word addresses!) This exercise examines the impact of different cache designs, specifically comparing associative caches to the direct-mapped caches from section 5.2. For these exercises, refer to the table of address streams shown in Exercise 5.3 (I'm reincluding them below - Tom).
|Virtual Address Size||Page Size||Page Table Entry Size|
|a.||32 Bits||4 KB||4 bytes|
|b.||64 Bits||16 KB||8 bytes|
Given the parameters in the table above, calculate the total page table size for a system running five applications that utilize half of the memory available
5.12.1-5 In this exercise, we will examine how replacement policies impact miss rate. Assume a two-way set-associative cache with four blocks. You may find it helpful to draw a table like those found on page 483 to solve the problems in this exercise, as demonstrated below on the address sequence "0,1,2,3,4".
|Address of Memory Block Accessed||Hit or Miss||Evicted Block||Set 0||Set 0||Set 1||Set 1|
The following table shows address sequences